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Preparation method and structure of sic MOSFET power device with high temperature resistance and low power consumption

A power device and low power consumption technology, applied in the field of microelectronics, can solve the problems that restrict the development of SiC power devices, device electrode failure, galvanic corrosion, etc., to improve channel mobility, improve interface characteristics, and increase high temperature resistance performance effect

Active Publication Date: 2019-05-24
北京北科控股有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

When the Al electrode doped with various metal elements is invaded by water vapor, galvanic corrosion sometimes occurs, resulting in the failure of the device electrode, and the metal electrode will melt at high temperature, which seriously restricts SiC. Development of Power Devices

Method used

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  • Preparation method and structure of sic MOSFET power device with high temperature resistance and low power consumption
  • Preparation method and structure of sic MOSFET power device with high temperature resistance and low power consumption
  • Preparation method and structure of sic MOSFET power device with high temperature resistance and low power consumption

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Embodiment 1

[0048] See figure 1 , figure 1 It is a schematic diagram of a method for manufacturing a SiC MOSFET power device with high temperature resistance and low power consumption provided by an embodiment of the present invention. The preparation method of the present invention can be used to prepare SiC MOSFET power devices with high temperature resistance and low power consumption. Specifically, the method includes the following steps:

[0049] Step 1, growing an N-drift layer on the SiC substrate;

[0050] Step 2, preparing a P well in the N-drift layer;

[0051] Step 3, preparing an N+ source region and a P+ contact region in the P well;

[0052] Step 4, sequentially preparing a first isolation dielectric layer, a gate and a second isolation dielectric layer on the P well including the N+ source region and the P+ contact region and the N-drift layer;

[0053] Step 5, preparing ohmic contact holes on the surface of the N+ source region and the P+ contact region;

[0054] Step...

Embodiment 2

[0077] See Figure 2a-2m , Figure 2a-2m A process schematic diagram of a MOSFET with high temperature resistance and low power consumption provided by an embodiment of the present invention. On the basis of the foregoing embodiments, this embodiment focuses on a detailed description of the process flow, specifically including the following steps:

[0078] Step 1. Select a SiC substrate 2 and grow an N − drift layer 3 on the SiC substrate 2 .

[0079] Such as Figure 2a As shown, the SiC substrate 2 is selected, the SiC substrate 2 is cleaned by RCA cleaning standard, and then the N-drift layer 3 doped with nitrogen ions is epitaxially grown on the surface of the SiC substrate 2, wherein the nitrogen ion doping concentration is 1 ×10 15 cm -3 , the thickness is 8μm, the epitaxy temperature is 1570°C, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is liquid nitrogen.

[0080] Step 2, performing mu...

Embodiment 3

[0118] See image 3 , image 3 A schematic structural diagram of a SiC MOSFET power device with high temperature resistance and low power consumption provided by an embodiment of the present invention. A kind of SiCMOSFET power device with high temperature resistance and low power consumption proposed by the present invention comprises:

[0119] Drain electrode 1, SIC substrate 2, N-drift layer 3, P well 4, N+ source region 5, P+ contact region 6, first isolation dielectric layer 8, crystal silicon gate 9, second isolation dielectric layer 10, source The pole ohmic contact metal layer 11 , the source copper graphene electrode 12 , and the drain ohmic contact metal layer 13 , wherein the N+ source region 5 and the P+ contact region 6 are located in the P well 4 .

[0120] Preferably, the substrate is a SiC substrate 2 .

[0121] Preferably, the convex region above the SiC substrate 2 is an N-drift layer 3 with a thickness of 8 μm.

[0122] Preferably, the P well 4 is a regi...

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Abstract

The invention relates to a fabrication method and structure of a SiC metal-oxide-semiconductor field-effect transistor (MOSFET) power device resistant to high temperature and with low power consumption. The fabrication method comprises the steps of growing an N-drift layer on a SiC substrate; fabricating P wells in the N-drift layer; fabricating an N+ source region and a P+ contact region in eachP well; sequentially fabricating a first isolation dielectric layer, a grid and a second isolation dielectric layer; forming ohmic contact holes in surfaces of the N+ source region and the P+ contactregion; fabricating source ohmic contact metal layers in the ohmic contact holes; fabricating source copper graphene electrodes on the source ohmic contact metal layers and the second isolation dielectric layer; and sequentially fabricating a drain ohmic contact metal layer and a drain electrode on a back surface of the SiC substrate, and finally, forming the SiC MOSFET power device resistant to high temperature and with low power consumption. In the SiC MOSFET power device provided by the embodiment of the invention, a phosphorus passivation effect is formed on an interface by phosphorus ioninjection combined with low-temperature oxidization, a source electrode employs a copper graphene composite material, the high-temperature resistance of the device is improved, and the power consumption of the device is reduced.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and relates to a preparation method and structure of a SiC MOSFET power device with high temperature resistance and low power consumption. Background technique [0002] Silicon carbide (SiC) has become one of the most advantageous semiconductor materials for manufacturing high-temperature, high-power electronic devices due to its excellent physical, chemical and electrical properties, and has a power device quality factor much greater than that of Si materials. The research and development of SiCMOSFET power devices began in the 1990s. It has a series of advantages such as high input impedance, fast switching speed, high operating frequency, high temperature and high pressure resistance, and has been used in switching regulated power supplies, high-frequency heating, automotive electronics, and power amplifiers. has been widely applied. [0003] For the electrode fabrication of SiC MOSF...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/04H01L29/78H01L29/45
CPCH01L21/0485H01L29/45H01L29/66068H01L29/7802
Inventor 侯同晓邵锦文贾仁需元磊汤晓燕
Owner 北京北科控股有限公司
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