Signal detector

Abstract

The invention discloses a signal detector which includes a signal input terminal, N first resistors, (N-1) second resistors, a third resistor, M voltage-to-current units and a collection unit. A firstterminal of a 1st first resistor is coupled to the signal input terminal. A first terminal of an ith first resistor is coupled to a second terminal of an (i-1)th first resistor. A first terminal of akth second resistor is coupled to a second terminal of a kth first resistor. A second terminal of each second resistor is coupled to a reference voltage terminal. The third resistor is coupled between the reference voltage terminal and a second terminal of an Nth first resistor. Each voltage-to-current unit is coupled to a first terminal of a corresponding first resistor for converting a corresponding detection voltage to detection current. The collection unit is coupled to the M voltage-to-current units for generating a detection signal according to at least the M detection currents.

Description

technical field [0001] The present invention relates to a signal detector, in particular to a device that can receive a set of voltages at a set of nodes of a circuit, convert the set of voltages into a set of currents, and collect the set of currents to generate a detection signal signal detector. Background technique [0002] In the field of wireless communication, the performance of the receiver is crucial. Currently available receiver structures may include a group of amplifiers connected in a cascade structure, wherein the input end of the amplifier of the first stage may be connected to an antenna to receive a received signal. For example, when the amplifiers used are differential amplifiers, each amplifier may have two input terminals and two output terminals. According to the current receiver architecture, the two input terminals of each amplifier can be coupled to a corresponding rectifier, therefore, the existing receiver architecture can have multiple rectifiers...

AI Technical Summary

Problems solved by technology

In order to increase the bandwidth, each stage amplifier can be selected as a high-bandwidth amplifier, but this will cause excessive power consumption

In addition, since the nodes of each stage of amplifiers correspond to different bandwidths, amplifiers with larger bandwidths should be selected for the later stage amplifiers, so it is difficult to achieve the symmetry of the amplifiers, which is not conducive to the design

In addition, when the gain of each amplifier is As, the gain of N amplifiers connected in series can be At, and the relationship can be At=(As) N , so the gain error (gain error) of amplifiers at all levels will accumulate step by step, resulting in the accuracy of gain being easily affected by temperature or process variation.

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