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Single event hardening-based programmable double-data-rate register circuit and control method

A single-particle reinforcement, double data technology, applied in the field of integrated circuits, can solve the problems of user function interruption, difficult to meet high-speed transmission, area requirements, etc.

Active Publication Date: 2018-07-27
BEIJING MXTRONICS CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] On the other hand, due to the influence of the spatial single event effect, the data in the programmable user register will be single-event flipped, causing errors in user stored data. If the programmable user register with single-event flipping is used as a key state machine, it will Make this user function interrupt
[0004] Traditional single-event hardening methods use dual-mode redundancy, triple-mode redundancy, etc. to harden memories and flip-flops, but have limited hardening capabilities for programmable logic devices
At the same time, these programmable user registers need to be able to work at a very high data transfer rate, using traditional hardening methods in double data rate registers will bring a huge area requirement, and it is difficult to meet the requirements of high-speed transmission

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  • Single event hardening-based programmable double-data-rate register circuit and control method

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Embodiment Construction

[0080] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0081] The basic idea of ​​the present invention is: a single particle reinforced programmable double data rate register circuit, including three reinforced registers with double redundant interlock structure, three clock control switches, three clock pulse generation circuits, a data Control switch, a data holding circuit with double redundant interlock structure. The single particle reinforcement design of the register storage unit is realized by using a circuit with a dual redundant interlock structure for the traditional latch. On this basis, multiple dual redundant circuits are controlled by adding a clock generation circuit, a data multiplexer and a data retention circuit. The register timing of the multi-interlock structure can realize the double data rate register function of various modes. By adjusting the generated clock pu...

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Abstract

The invention discloses a single event hardening-based programmable double-data-rate register circuit and a control method. A circuit with a dual-redundancy interlocking structure is adopted for a conventional latch to realize single event hardening design of a register storage unit; and based on this, a clock generation circuit, a data multiplexer and a data retaining circuit are added for controlling a time sequence of multiple registers with dual-redundancy interlocking structures, so that multi-mode double-data-rate register functions can be realized. A single event hardening index is improved by three orders of magnitude in comparison with that of a conventional register, and programmable functions of a level latch, a single-data-rate edge trigger, a reverse-edge-mode double-data-rateedge trigger, a same-edge-mode double-data-rate edge trigger and the like can be realized, so that higher flexibility, better time sequence performance and extremely high anti-single event hardeningindex are achieved during use of a programmable user register by a user.

Description

technical field [0001] The invention relates to a single-particle hardened programmable double data rate register circuit and a control method, in particular to a programmable single-particle hardened register circuit and a control method optimized for the application requirements of programmable logic devices, belonging to an integrated circuit field. Background technique [0002] Programmable logic devices have the advantages of high flexibility, low cost, and short cycle time. They can greatly shorten the product development cycle and minimize risks. They have become core components in the integrated circuit industry. The programmable user register is the core circuit in the programmable logic device to realize the user's sequential logic function, and can be programmed to realize various sequential functions according to the user's needs. [0003] On the other hand, due to the influence of the spatial single event effect, the data in the programmable user register will ...

Claims

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Application Information

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IPC IPC(8): G11C7/10G11C7/24
CPCG11C7/106G11C7/1087G11C7/24
Inventor 陈雷倪劼李琦孙华波王文锋郭琨孙健爽刘亚泽钱涛涛
Owner BEIJING MXTRONICS CORP
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