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Overlay mark, and overlay measurement method and semiconductor device manufacturing method using same

An alignment mark, one-to-one technology, applied in the direction of semiconductor devices, semiconductor/solid-state device components, and originals for optomechanical processing, can solve problems such as reducing accuracy and straining alignment mark images, and achieve improved accuracy degree of effect

Active Publication Date: 2018-07-31
AUROS TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

like figure 1 The mark shown has the following problem: Since a plurality of rods 2 are arranged at equal intervals, when the intensity of the signal is weak, it will be as follows: figure 2 The error shown is read when the image is analyzed shifted one cycle to the left
In this case, there is also a problem that the alignment mark image obtained by the chromatic aberration due to the difference in the refractive index of each wavelength of the light source;
The strain of such an image becomes the reason for reducing the accuracy of the alignment determination

Method used

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  • Overlay mark, and overlay measurement method and semiconductor device manufacturing method using same
  • Overlay mark, and overlay measurement method and semiconductor device manufacturing method using same
  • Overlay mark, and overlay measurement method and semiconductor device manufacturing method using same

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Embodiment Construction

[0023] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. However, the embodiments of the present invention can be modified into other various forms, and the scope of the present invention should not be construed as being limited to the above-mentioned embodiments. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Therefore, in order to emphasize clearer description, the shapes and the like of elements in the drawings are exaggerated, and elements denoted by the same symbols in the drawings mean the same elements.

[0024] image 3 It is a top view of an example of the alignment mark of this invention.

[0025] refer to image 3 , an embodiment of the alignment mark 100 of the present invention includes a first alignment structure 10 and a second alignment structure 20 . The alignment mark 100 can be formed on the scribe line of the...

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Abstract

The present invention relates to an overlay mark, and an overlay measurement method and a semiconductor device manufacturing method using the same. The present invention provides an overlay mark for determining the relative shift between two successive pattern layers or between two or more patterns separately formed on a single layer, the overlay mark comprising: a first overlay structure that includes a pair of first bars facing one another and extending in a first direction, and a pair of second bars facing one another and extending in a second direction that is orthogonal to the first direction; and a second overlay structure that includes a plurality of pairs of third bars parallel to the first bars, and a plurality of pairs of fourth bars parallel to the second bars, wherein the gapsbetween neighbouring third bars are different from one another, and the gaps between neighbouring fourth bars are different from one another. The overlay mark according to the present invention has different gaps between bars, thereby being capable of minimising the occurrence of errors during image analysis.

Description

technical field [0001] The present invention relates to an alignment mark, an alignment measurement method using it, and a semiconductor device manufacturing method. Background technique [0002] On the semiconductor substrate, a plurality of pattern layers are sequentially formed. And, a circuit of one layer is formed by dividing into two patterns by double patterning or the like. Only when such a patterned layer or multiple patterns of one layer are accurately formed to a predetermined position can a desired semiconductor element be manufactured. [0003] Therefore, in order to confirm whether the pattern layer is accurately aligned, an alignment mark formed simultaneously with the pattern layer is used. [0004] The method of determining alignment using the alignment marks is as follows. First, the pattern layer formed in the previous process (eg, etching process) is used as the pattern layer, and at the same time, one structure that is a part of the alignment mark is ...

Claims

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Application Information

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IPC IPC(8): G03F7/20G03F9/00G03F1/42H01L23/544
CPCG03F1/42G03F7/20G03F9/00H01L23/544
Inventor 张贤镇河昊澈李吉洙
Owner AUROS TECH