Data Exchange Method for Grid Storage

Abstract

The exchange mode and addressing mode of data and storage unit or other device units applied in the fields of electronic computer technology, electronic communication and database. The chip is manufactured using a three-dimensional structure, formed by lines intersecting each other in three dimensions. A chip unit element is provided at every intersection of three lines. Each line is connected to a specific chip unit element (such as a header, or an inlet, or an outlet). All circuits are located outside the surface of the three-dimensional crystal plane of the chip. Unit switching circuits are formed on some crystal planes, and charged particle currents or electromagnetic radiation streams are scanned on other crystal planes according to prescribed procedures, and independent lines or line groups and closed circuits are selected. In this way, the increase in the number of crystal layers does not lead to an increase in the density of vertical lines, thereby greatly increasing the number of chip units and reducing costs. This approach simplifies the swapping of cells and does not require switching circuits on all facets of the 3D crystal.

Description

technical field [0001] The present invention belongs to the field of electronic information storage devices, and is also applicable to processors or other computer technology devices, communication networks and independent databases. Background technique [0002] Leading companies in the field of memory chip manufacturing, such as Samsung and SanDisk, have begun to produce a new generation of flash memory 3D Vertical NAND (V-NAND), and Intel is producing stacked chips with a three-dimensional structure (http: / / compulenta.computerra.ru / tehnika / microelectronics / 10011567 / ; http: / / www.cybersecurity.ru / hard / 122063.html; www.3dnews.ru / 918582). [0003] The currently known new technique is to align the crystals vertically. In this way, the microchip has a spatial structure, which means that the amount of information stored in the chip and the number of components per unit area will be greatly increased. A significant disadvantage of this stack structure is that as the number of ...

AI Technical Summary

Problems solved by technology

A significant disadvantage of this stack structure is that as the number of stack layers increases, the circuit density associated with individual cells and layers with logic switching circuits also increases dramatically

This limits the increase in the number of layers, which in turn limits the increase in storage capacity and the number of chip components