Digital circuit fault injection method based on simulation

Abstract

The invention discloses a digital circuit fault injection method based on simulation. The digital circuit fault injection method comprises the steps that a target signal list is created, target signals are obtained, and faults are injected. The adopted technical scheme supports flexible operation of multiple signal lists, fault injection types can be set, the duration time of faults can be set, and random fault injection and multi-point fault injection can be also achieved except fault injection of designated signals. The digital circuit fault injection method is based on simulation, does notneed to modify VHDL models, is directly achieved in Test Bench (TB) by adopting simple, short efficient codes and can simply and quickly support the verification of reliability design. The method is simple and easy to carry out, can be quickly achieved, is flexible to use, can effectively simulate fault phenomena such as internal level turnover of a processor under an actual environment.

Description

technical field [0001] The invention belongs to the technical field of digital circuits, and relates to a simulation-based digital circuit fault injection method. Background technique [0002] In recent years, with the continuous shrinking of the feature size of integrated circuits, the performance of processors has been rapidly improved. However, such high integration, low threshold voltage and high operating frequency make processors less sensitive to crosstalk, electromagnetic interference and particle radiation. The influence of the processor is more sensitive, and it is easy to cause various failures of the processor, which poses a severe challenge to the reliability of the processor. In order to overcome these challenges, it is necessary to carry out a fault-tolerant design on the processor, take appropriate protective measures to enhance circuit reliability, and ensure the normal operation of various functions of the system as much as possible. [0003] In processor ...

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Problems solved by technology

[0004] The current research has designed a lot of fault injection platforms for front-end simulation, and these platforms are systematic, can provide a variety of fault injection mechanisms, and automatically analyze the operation of the processor after fault injection; but because of the current The comprehensive and systematic method leads to the fact that such a set of fault injection and analysis platform needs to invest more manpower and material resources to complete its development, and the development cycle of the system is also longer, so it cannot be put into use in the early stage of front-end design, or in the Due to the imperfection of the scheme itself, it is impossible and unnecessary to use such a systematic verification and evaluation scheme to test the fault-tolerant effect of each design point in the scheme demonstration and scheme realization phases of the reinforcement design.

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