High-speed pulse output duty ratio automatic regulation method based on CPLD

Abstract

The present invention discloses a high-speed pulse output duty ratio automatic regulation method based on a CPLD (Complex Programmable Logic Device). The method concretely comprises the following steps of: S1: depositing a high-speed pulse output duty ratio emitted by a high-speed pulse output EBRSRAM block in the CPLD into a plurality of frequency and duty ratio registers so understand the emitted high-speed pulse output duty ratio; and S2: allowing the high-speed pulse output EBRSRAM block to emit high-speed pulse and act to an MOS tube output module, wherein the output high-speed pulse frequency duty ratio is output according to a preset value to directly control the output of the MOS tube output module. The high-speed pulse output duty ratio automatic regulation methods output frequency values and duty ratio values read in the high-speed pulse output EBRSRAM block registers through a frequency and duty ratio state machine and compares the frequency values and duty ratio values readin the high-speed pulse output EBRSRAM block registers through the frequency and duty ratio state machine with frequency values and duty ratio values of the registers in the high-speed pulse output feedback EBRSRAM block so as to achieve automatic regulation of the high-speed pulse duty ratio of the PLC (Programmable Logic Controller) controller, reduce the deviation of the output high-speed pulse duty ratio and a preset value and ensure the high-speed pulse output of the PLC.

Description

technical field [0001] The invention relates to the technical field of industrial automation, in particular to a method for automatically adjusting the duty ratio of high-speed pulse output based on CPLD. Background technique [0002] PLC (ProgrammableLogicController, programmable logic controller) is widely used in various automation control fields. It is a digital computing operation electronic system specially designed for application in industrial environments. It uses a programmable memory and stores it internally. Instructions to perform operations such as logic operations, sequence control, timing, counting, and arithmetic operations, and to control various types of mechanical equipment or production processes through digital or analog input and output; one of the main functions of PLC is to achieve different frequencies and The high-speed pulse output of duty cycle is to realize the high-speed pulse output of PLC. [0003] At present, in order to realize the high-sp...

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Problems solved by technology

[0004] The object of the present invention is to provide a kind of method based on the automatic adjustment of high-speed pulse output duty ratio of CPLD, read the frequency value and the duty ratio value of output from the high-speed pulse output EBRSRAM block register by frequency and duty ratio state machine and compare with The high-speed pulse output feeds back the frequency value and the duty cycle value of the register in the EBRSRAM block to compare, so as to realize the advantages of the PLC controller automatically adjusting the high-speed pulse duty cycle, and solve the problem of the junction capacitance of the MOS tube that leads to the final output of the high-speed pulse output There is a large deviation between the duty cycle and the preset value, and at the same time setting more registers will consume a lot of CPLD lookup table resources

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