High-speed pulse output duty ratio automatic regulation method based on CPLD

A technology for outputting duty cycle and high-speed pulses, which is applied in control/regulation systems, program control in sequence/logic controllers, instruments, etc., can solve the problems of CPLD lookup table resource consumption and deviation, and ensure high-speed pulse output , reduce deviation, and facilitate adjustment

CN108459554AInactive Publication Date: 2018-08-28桂林市华茂欧特科技有限公司
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Publication Date
2018-08-28
Estimated Expiration
Not applicable · inactive patent

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Abstract

The present invention discloses a high-speed pulse output duty ratio automatic regulation method based on a CPLD (Complex Programmable Logic Device). The method concretely comprises the following steps of: S1: depositing a high-speed pulse output duty ratio emitted by a high-speed pulse output EBRSRAM block in the CPLD into a plurality of frequency and duty ratio registers so understand the emitted high-speed pulse output duty ratio; and S2: allowing the high-speed pulse output EBRSRAM block to emit high-speed pulse and act to an MOS tube output module, wherein the output high-speed pulse frequency duty ratio is output according to a preset value to directly control the output of the MOS tube output module. The high-speed pulse output duty ratio automatic regulation methods output frequency values and duty ratio values read in the high-speed pulse output EBRSRAM block registers through a frequency and duty ratio state machine and compares the frequency values and duty ratio values readin the high-speed pulse output EBRSRAM block registers through the frequency and duty ratio state machine with frequency values and duty ratio values of the registers in the high-speed pulse output feedback EBRSRAM block so as to achieve automatic regulation of the high-speed pulse duty ratio of the PLC (Programmable Logic Controller) controller, reduce the deviation of the output high-speed pulse duty ratio and a preset value and ensure the high-speed pulse output of the PLC.
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Description

technical field

[0001] The invention relates to the technical field of industrial automation, in particular to a method for automatically adjusting the duty ratio of high-speed pulse output based on CPLD. Background technique

[0002] PLC (ProgrammableLogicController, programmable logic controller) is widely used in various automation control fields. It is a digital computing operation electronic system specially designed for application in industrial environments. It uses a programmable memory and stores it internally. Instructions to perform operations such as logic operations, sequence control, timing, counting, and arithmetic operations, and to control various types of mechanical equipment or production processes through digital or analog input and output; one of the main functions of PLC is to achieve different frequencies and The high-speed pulse output of duty cycle is to realize the high-speed pulse output of PLC.

[0003] At present, in order to realize the high-sp...

Examples

Embodiment 1

[0026] refer to figure 1 , a method for automatically adjusting the duty cycle of a high-speed pulse output based on CPLD, specifically comprising the following steps:

[0027] S1: The high-speed pulse output duty cycle emitted by the high-speed pulse output EBRSRAM block in the CPLD will first be stored in multiple frequency and duty cycle registers, so as to know the high-speed pulse output duty cycle emitted;

[0028] S2: High-speed pulse output The EBRSRAM block emits high-speed pulses to act on the MOS tube output module, and the duty cycle of the output high-speed pulse frequency is output according to the preset value to directly control the output of the MOS tube output module;

[0029] S3: The high-speed pulse output duty ratio output by the MOS transistor output module will act on the high-speed pulse output feedback EBRSRAM block in the CPLD, and the high-speed pulse output feedback EBRSRAM block will latch the high-speed pulse output duty ratio output by the MOS tr...

Embodiment 2

[0034] refer to figure 2 , a method for automatically adjusting the duty cycle of a high-speed pulse output based on CPLD, the method steps are the same as in embodiment 1, certainly, an interrupt module is also included in the CPLD, and the output end of the interrupt module is connected with a PLC micro-controller device, figure 2 The MCU in the article is the PLC microcontroller mentioned in the article. The interrupt module generates an interrupt signal for the frequency register and the duty ratio state machine to the PLC microcontroller. The PLC microcontroller then configures the corresponding high-speed pulse output EBRSRAM block according to the interrupt signal. .