A virtual ground flash memory reading circuit

Abstract

The invention discloses a virtual grounding flash memory reading circuit, which comprises a virtual grounding flash memory array, a column decoding circuit, a voltage control circuit and a sensitive amplifier, wherein the voltage control circuit is used for connecting the other ends of the column decoding circuit corresponding to the two bit lines of the adjacent storage unit of the selected storage unit and regulating the bit line voltage of the two bit lines after the two bit lines to a state of being uniform to the bit line voltage of the selected storage unit so as to avoid the read-out current loss or interference. The read operation output accuracy of the virtual grounding flash memory circuit can be improved.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a virtual ground flash memory reading circuit. Background technique [0002] figure 1 It is a schematic circuit diagram of a prior art virtual ground flash memory reading circuit, such as figure 1 As shown, the virtual ground flash memory reading circuit includes a virtual ground flash memory array 10 , a column decoding circuit 20 , a voltage control circuit 30 and a sense amplifier 40 . The virtual ground flash memory array 10 is composed of several virtual ground storage units for storing information, and the illustration only shows the selected storage unit and its adjacent four storage units Cell0, Cell1, Cell2, and Cell3; the column decoding circuit 20 is composed of NMOS transistors Composed of M00 / M10, M1 / M11, M02 / M12, and M03 / M13, it is used to transmit the readout current of the selected memory cell to the input terminal of the sense amplifier 40 under the control of t...

AI Technical Summary

Problems solved by technology

During the read operation, since the currents flowing through the decoding array MOS transistors M01 / M11 and M02 / M12 of the column decoding circuit 20 are different in size, the bit line voltage of the selected memory cell is the voltage at point F (bit line BL1 voltage) There is a voltage difference between the bit line voltage of the adjacent memory cell of the selected memory cell, that is, the voltage of point G (voltage of bit line BL2), and the voltage of point F is lower than the voltage of point G, and the side leakage Ileak flowing from point G to point F appears , the current Isense read by the sense amplifier is not equal to the read current Icell of the selected memory cell, but less than Icell, that is, Isense=Icell-Ileak, which affects the read margin and reduces the accuracy of the output of the flash memory read operation

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