Test optimization method of integrated circuit wafer

A technology of wafer testing and optimization method, which is applied in the direction of electronic circuit testing, automatic testing system, and electrical measurement. It can solve the problems of low wafer testing efficiency, improve testing efficiency, reduce testing time, and reduce the number of needles. Effect

Active Publication Date: 2018-09-11
SINO IC TECH
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Problems solved by technology

[0005] The present invention aims at the problem of low wafer test efficiency, and proposes an integrated circuit wafer test optimization method, which is applied in the integrated circuit wafer test process, by specifying the die coordinates to be tested in advance and storing them in the test system In the test p

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  • Test optimization method of integrated circuit wafer
  • Test optimization method of integrated circuit wafer

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[0024] Different types of chips and different manufacturing processes have a huge difference in wafer yield. It is possible that the yield of A product is 99%, the yield of B product is 70%, and the yield of C product is only 20%-30%, but the tests are all necessary All die testing of the entire wafer is completed. For the A product, 1% of defective products need to be picked out, but the test time for the entire film is required, and the test efficiency and cost ratio are poor.

[0025] From the statistics of a large number of wafer test results, there is a large correlation between adjacent die failures, that is, if the die of the (X=100, Y=100) coordinate is in the failed state, and the die is the center, There is a greater probability of failure of the surrounding 8 die.

[0026] By pre-designating the coordinates of the die to be tested in the wafer and storing it in the test system, the designated die is tested during the test and adjusted in real time according to the test ...

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Abstract

The invention relates to a test optimization method of an integrated circuit wafer, and is applied to a test process of the integrated circuit wafer. The method includes: designating a die coordinatein need of a test on the wafer in advance and storing the coordinate in a test system, then testing the pre-designated die according to a design pattern in a test process and adjusting the range of the pre-designated coordinate in real time according to a current die test result, and finally obtaining a required test coordinate pattern to cover the most invalid die quantity with a most optimized scheme so that the test time is reduced, the test efficiency is improved, the usage frequency of test hardware is reduced, and the service lifetime is prolonged. According to the method, through propercoverage quantity calculation, a small quantity of FAIL chips flowing to package are obtained, and the packaging cost is not increased; besides, the test frequency of a probe card is reduced, and theservice lifetime of the hardware is prolonged.

Description

technical field [0001] The invention relates to a test and detection technology, in particular to an integrated circuit wafer test optimization method. Background technique [0002] ATE (Automatic Test Equipment): A semiconductor integrated circuit (IC) automatic tester, used to test the integrity of integrated circuit functions. Wafer: Wafer refers to the silicon wafer used in the production of silicon semiconductor integrated circuits. Because of its circular shape, it is called a wafer; it can be processed into various circuit element structures on the silicon wafer, and becomes a circuit with specific electrical properties. Functional IC products. Die: An independent integrated circuit chip on a wafer. [0003] Due to the advancement of integrated circuit design and manufacturing technology, the size of chips is getting smaller and smaller, but the size of silicon wafers has increased from 200mm to 300mm, and the number of chips that can be accommodated on a single waf...

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Application Information

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IPC IPC(8): G01R31/28
CPCG01R31/2851G01R31/2831G01R31/2834G01R31/2891
Inventor 王华张志勇凌俭波祁建华刘远华季海英
Owner SINO IC TECH
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