Three-dimensional memory and its manufacturing method
A manufacturing method and memory technology, applied to semiconductor devices, electrical solid devices, electrical components, etc., can solve problems such as error-prone, increased failure analysis time, waste of FIB resources, etc., to reduce costs, improve work efficiency and positioning success rate Effect
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no. 1 Embodiment approach
[0044] This specific embodiment provides a three-dimensional memory, with Figure 1A It is a schematic top view structural diagram of the three-dimensional memory in the first specific embodiment of the present invention, with Figure 1B is a schematic top view of the block storage area in the first embodiment of the present invention, with figure 2 It is a schematic cross-sectional structure diagram of the three-dimensional memory in the first embodiment of the present invention.
[0045] In a three-dimensional memory, the large-sized block area (Giant Block) of each die (Die) contains multiple block storage areas (Block) arranged in an array, for example, 1024 block storage areas arranged in an array, Each block storage area also contains one or more array common sources (ACS). Since most of the block storage areas in the die are repetitive structures, and the array common sources in the block storage areas are also repetitive structures, so There is no clear distinction b...
no. 2 Embodiment approach
[0070] This specific embodiment provides a three-dimensional memory and its manufacturing method, with image 3 It is a top view structural diagram of the three-dimensional memory in the second specific embodiment of the present invention. For the same parts as the first specific embodiment, this specific embodiment will not repeat it, and the differences from the first specific embodiment will be mainly described below.
[0071] The sub-marks in this specific embodiment are located at the periphery of the gate line isolation groove area. like image 3 As shown, the block storage area 30 is divided into several finger storage areas 301 by the gate line separation area, and the array common source 302 is located in the gate line separation area. The sub-mark 35 is formed by extending from the end of the array common source 302 to a direction away from the gates of several layers.
[0072] The three-dimensional memory also includes an identification groove II communicating wi...
no. 3 Embodiment approach
[0076] This specific embodiment provides a three-dimensional memory and a manufacturing method thereof. For the same parts as the first specific embodiment, this specific embodiment will not repeat it, and the differences from the first specific embodiment will be mainly described below.
[0077] The sub-marker in this specific embodiment is located in the gate line isolation groove area. Specifically, the block storage area in the three-dimensional memory is divided into several finger storage areas by the gate line separation groove area; the array common source is filled in the gate line separation groove area, and the sub-mark is located in the array common source pole end.
[0078] The steps to form a sub-identity include:
[0079] Filling the conductive layer in the gate line separation groove area to form an array common source;
[0080] Etching the end of the common source of the array to form the submark.
[0081] In this specific implementation manner, the finger...
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