Semiconductor integrated circuit device

Abstract

Pads (21, 22, 23, 24, 25, 26) connected to nanowires (11, 12, 13, 14) in standard cell (1) comprising nanowire FETs (P11, P12, N11, N12) The nanowires (11, . . . ) are arranged in the X direction in which they extend with a prescribed center-to-center pitch (Pp). The cell width (Wcell) of the standard cell (1) is an integer multiple of the center-to-center pitch (Pp). In the case where the standard cells (1) are arranged to constitute the layout of the semiconductor integrated circuit device, the pads (21, . . . ) are regularly arranged in the X direction.

Description

technical field [0001] The present disclosure relates to a semiconductor integrated circuit device including a standard cell using a nanowire FET (Field Effect Transistor). Background technique [0002] It is known that there is a standard cell method as a method of forming a semiconductor integrated circuit on a semiconductor substrate. The standard cell method refers to a method in which basic cells with specific logic functions (such as inverters, latches, flip-flops, full adders, etc.) are prepared as standard cells in advance, and then a plurality of standard cells are arranged A way to design LSI chips by connecting these standard cells with wiring on a semiconductor substrate. [0003] A transistor that is a basic component of an LSI achieves an increase in integration, a decrease in operating voltage, and an increase in operating speed by reducing the gate length (scaling: scaling). However, in recent years, there has been a problem that excessive size reduction ca...

AI Technical Summary

Problems solved by technology

However, in recent years, there has been a problem that excessive downsizing causes off-current, which in turn causes a significant increase in power consumption

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