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Three-dimensional semiconductor device with isolated dummy pattern

A semiconductor and component technology, applied in the field of three-dimensional semiconductor components, can solve problems such as damage to three-dimensional semiconductor components

Active Publication Date: 2021-03-05
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Macrocyclic region R BR The larger the area, the greater the number of accumulated charges, especially in some structurally relatively fragile places (such as tips or edges), so the arc effect caused is more serious, resulting in damage to three-dimensional semiconductor components

Method used

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  • Three-dimensional semiconductor device with isolated dummy pattern
  • Three-dimensional semiconductor device with isolated dummy pattern
  • Three-dimensional semiconductor device with isolated dummy pattern

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0084] image 3 It is a top view of a three-dimensional semiconductor element according to the first embodiment of the present invention. Figure 4A for along image 3 The schematic cross-sectional view of the three-dimensional semiconductor element drawn by the section line 4A-4A'. Figure 4B for along image 3 A schematic cross-sectional view of the three-dimensional semiconductor element drawn on the section line 4B-4B'. A three-dimensional semiconductor device 2 of the first embodiment includes a substrate 20 having a first area A1 and a second area A2, wherein an array pattern (array pattern) P array formed in the first region A1. A stack structure (stack structure) has multi-layers (multi-layers) stacked on the substrate 20, the multi-layers include several layers of active layers (active layers) 212 (ex: conductive layer, such as polysilicon layer) and Insulating layers (ex: oxide layers) 213 are alternately disposed on the substrate 20 . The stack structure inclu...

no. 2 example

[0091] In the second embodiment, a proposed imaginary island pattern is the macrocyclic region R corresponding to the second region A2 BR with isolation region R I .

[0092] Figure 5 It is a top view of a three-dimensional semiconductor device according to the second embodiment of the present invention. Figure 6A for along Figure 5 A schematic cross-sectional view of the three-dimensional semiconductor element drawn by the section line 6A-6A'. Figure 6B for along Figure 5 A schematic cross-sectional view of the three-dimensional semiconductor element drawn on the section line 6B-6B'. The structures of the three-dimensional semiconductor elements 2 and 3 of the first embodiment and the second embodiment are similar, and the difference is that the three-dimensional semiconductor element 3 of the second embodiment further includes second dummy islands (second dummy islands) disposed on the substrate 20 above. Furthermore, Figure 5 , Figures 6A-6B with image 3 ,...

no. 3 example

[0097] In the third embodiment, a proposed imaginary island pattern is the macrocyclic region R corresponding to the second region A2 BR , isolation area R I and the surrounding area R Peri .

[0098] Figure 7 It is a top view of a three-dimensional semiconductor element according to the third embodiment of the present invention. Figure 8A for along Figure 7 The schematic cross-sectional view drawn by the section line 8A-8A' of the three-dimensional semiconductor element. Figure 8B for along Figure 7 The schematic cross-sectional view drawn by the section line 8B-8B' of the three-dimensional semiconductor element. Figure 8C for Figure 7 A three-dimensional schematic diagram of a semiconductor device. The three-dimensional semiconductor elements 3 and 4 of the second embodiment and the third embodiment are the same, except that the three-dimensional semiconductor element 4 of the third embodiment further includes a third dummy island (third dummy islands) 1 dumm...

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PUM

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Abstract

The invention discloses a three-dimensional semiconductor element with an isolation imitation pattern. Wherein, the three-dimensional semiconductor element includes: a substrate with a first region and a second region, and the second region is adjacent to and surrounds the first region, wherein an array pattern is formed in the first region (active region); a stack The layer structure has multiple layers stacked on the substrate, and the multiple layers include active layers (such as conductive layers) and insulating layers arranged alternately on the substrate. The stack structure includes a plurality of first stacks corresponding to the array pattern, and the first stacks are formed in the first area; and a plurality of second stacks are separately arranged in the second area, and these first stacks The second stack is the first stack that forms islands like the first quasi-island and surrounds the array pattern.

Description

technical field [0001] The present invention relates to a three-dimensional semiconductor element, in particular to a three-dimensional semiconductor element with an isolation dummy pattern. Background technique [0002] In the traditional manufacturing process of a three-dimensional semiconductor device (such as memory), it is necessary to use a deep trench etching (deep trench etching) step to cut and form bit lines or word lines (such as forming known BL-to-BL or WL -to-WL structure). Before the deep trench etching step, it is necessary to stack multiple conductive layers on a substrate (for example, formed above a substrate or in a recessed space forming the substrate), and then planarize the stacked layers. chemical process and deep trench etch process. During deep trench etching, charges from the plasma can accumulate at the conductive layer, causing damage and defects in the three-dimensional semiconductor device. [0003] figure 1 It is a top view of a traditiona...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02
CPCH01L27/0207H10B41/27H10B43/27
Inventor 叶腾豪洪敏峰胡志玮
Owner MACRONIX INT CO LTD