Multi-DDR controller management module based on AXI bus

Abstract

The invention discloses a multi-DDR controller management module based on an AXI bus, comprising N DDR controllers (N is more than 0), N switches (N is more than 0) and M port adapters (M is more than0), the port adapters are used for converting a read-write operation signal for each client into a read-write operation signal for one DDR controller by virtue of an all-pass network and the switchesaccording to a principle of equal distribution of bandwidth; the switches are used for exchanging and arbitrating read-write addresses and data of L (L is more than 0) clients by virtue of the all-pass network and the port adapters and outputting the arbitrated read-write addresses and data signals to the DDR controllers; and the DDR controllers perform a read-write access operation on the controlled DDR chips according to the read-write control signals. The multi-DDR controller management module possesses an efficient multi-DDR read-write access arbitrating and bandwidth balancing capabilities and a standard AXI interface, a user can conveniently perform multi-DDR access by virtue of the standard interface and can meet FPGA development requirements in the radar signal processing field.

Description

technical field [0001] The invention relates to the field of computer application technology, in particular to a multi-DDR controller management module based on the AXI bus. Background technique [0002] With the development of digital phased array radar, the working bandwidth of radar products is increasing, the number of channels after digital synthesis is increasing, the algorithm processing flow of radar signal processing is becoming more and more complex, and the processing accuracy is getting higher and higher. These have become the inevitable trend of radar development. [0003] The increase in radar operating bandwidth and the number of channels directly lead to a sharp increase in the input data rate of the signal processing system. Taking a digital radar with a sampling rate of 50M, 16 channels, and input IQ of 16 bits as an example, the input data rate is as high as 3200MB / s. Considering the read and write efficiency of DDR, the access bandwidth of a single DDR...

AI Technical Summary

Problems solved by technology

The floating-point data type leads to the expansion of the original data bit width, which further increases the access bandwidth during the operation

[0006] In the FPGA implementation process of signal processing, the arbitration of parallel reading and writing of multiple sets of DDRs, the balance of access bandwidth of multiple sets of DDRs, and the space management of multiple sets of DDRs are the difficulties in the design of signal processing and memory access. Will consume a lot of time and energy of the signal processing engineer

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