Communication structure and method between upper computer and InterBus module based on FPGA

Abstract

The invention discloses a communication structure and method between a upper computer and an InterBus module based on FPGA, including a PCIE interface, a FPGA mainboard and the InterBus module. The PCIE interface is connected with the FPGA mainboard and a PCIE slot of the upper computer. The InterBus module achieves correspondence with an external device and is connected with the FPGA mainboard through a DPRAM parallel interface module. Data packets sent by the upper computer are unpacked by the FPGA mainboard and then transmitted to the InterBus module through the DPRAM parallel interface module. On the contrary, the InterBus module transmits the data packets to the FPGA mainboard through the DPRAM parallel interface module. The FPGA mainboard is packaged as needed and transmits data after packaged to the upper computer through the PCIE interface. The communication structure and method between the upper computer and the InterBus module based on FPGA can greatly shorten transmission time and jitter time.

Description

technical field [0001] The invention relates to the field of communication interface design, in particular to a communication structure and method of an FPGA-based upper computer and an InterBus module. Background technique [0002] In the communication between equipment and equipment in the field of industrial field, there is a large amount of data interaction, as well as different types of bus interfaces, one of which is the InterBus bus protocol, which is a sensor / regulator bus system, which is especially suitable for industrial purposes and can provide The consistent network interconnection from the control-level equipment to the bottom limit switch is especially used in the robot communication process. The communication between the robot and the industrial computer is completed through the InterBus bus. For example, the IBSPCI RI-LK of Phoenix realizes this function. However, this interface has problems such as long transmission time, low transmission rate, and large de...

AI Technical Summary

Problems solved by technology

[0003] PCI-Express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard designed to replace the old PCI, PCI-X and AGP bus standards. It belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices Allocate exclusive channel bandwidth and do not share bus bandwidth. InterBus cannot be directly connected to PCIE in the prior art. This technical solution aims to build communication between InterBus and PCIE to shorten data transmission time and jitter time

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