Flip-chip method

A flip-chip and barrier layer technology, which is applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve the problems of poor solder layer quality and easy connection, and achieve the effects of improving quality, avoiding short circuits, and avoiding collapse

Active Publication Date: 2018-11-20
NANTONG FUJITSU MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, in the existing flip-chip method, the quality of the solder layer is poor, and adjacent solder layers are easily connected together

Method used

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Experimental program
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Embodiment Construction

[0021] As mentioned in the background, the flip-chip method formed in the prior art will result in poor quality of the solder layer, and adjacent solder layers are easily connected together.

[0022] Figure 1 to Figure 2 is a schematic diagram of the structure of the flip-chip method.

[0023] refer to figure 1 , providing a semiconductor chip 100, a conductive connecting column 110 and a carrier plate 130, the conductive connecting column 110 has an opposite first surface and a second surface; the conductive connecting column 110 is fixed on the surface of the semiconductor chip 100, the first Facing the semiconductor chip 100; the solder ball 140 is fixedly arranged on the second surface of the conductive connection column 110; after that, the semiconductor chip 100, the conductive connection column 110 and the solder ball 140 are placed on the surface of the carrier board 130, and the solder ball 140 is connected to the surface of the carrier plate 130. The carrier board...

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Abstract

Disclosed is a flip-chip method. The flip-chip method comprises the steps that a semiconductor chip and a conductive connecting column are provided, wherein the conductive connecting column is provided with a first surface and a second surface which are opposite to each other; the conductive connecting column is fixed on the surface of the semiconductor chip, and the first surface faces the semiconductor chip; a first barrier layer is formed on the side wall of the conductive connecting column, and the first barrier layer is exposed out of the second surface of the conductive connecting column; a carrier plate is provided; a solder column is formed on the surface of the carrier plate; a second barrier layer is formed, wherein the second barrier layer is positioned on the surface of the carrier plate around the solder column; after the first barrier layer and the second barrier layer are formed, the solder column is in contact with the second surface, and the conductive connecting column is located on the solder column; after the solder column is in contact with the second surface, reflow soldering is carried out, and the solder column is processed to form a solder layer. Accordingto the method, the quality of the solder layer is improved, and the adjacent solder layers are prevented from being connected together.

Description

technical field [0001] The invention relates to the packaging field, in particular to a flip-chip method. Background technique [0002] The flip chip process is not only a chip interconnection technology, but also an ideal chip bonding technology. As early as more than 50 years ago, IBM (International Business Machines Corporation) has developed and used this technology. But until recent years, flip-chip has become a frequently used package formation in the field of high-end devices and high-density packaging. At present, the application range of flip-chip packaging technology is becoming wider and wider, and the packaging forms are becoming more diversified, and the requirements for flip-chips are also increasing. [0003] However, in the existing flip-chip method, the quality of the solder layer is poor, and adjacent solder layers are easily connected together. Contents of the invention [0004] The problem solved by the present invention is to provide a flip-chip met...

Claims

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Application Information

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IPC IPC(8): H01L21/60
CPCH01L24/81H01L2224/81007H01L2224/81009H01L2224/81815H01L2224/11H01L2224/16225H01L2224/16245H01L2924/15311H01L2924/181H01L2924/00012
Inventor 石磊
Owner NANTONG FUJITSU MICROELECTRONICS
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