Clock Data Recovery Lock Detection Circuit Adapting to Variable Bandwidth in Serial Communication

Abstract

The invention belongs to the technical field of integrated circuit design, and is a clock data recovery locking detection circuit adapting to variable bandwidth in high-speed serial communication. The lead / lag signals output by the filter are respectively input to two sets of shift registers and used as mutual reset signals . The output of the two groups of shift registers is logically ORed to obtain the CDR_LOCK signal. For filters with different bandwidths, the CDR lock detection circuit of the present invention automatically adjusts the resolution of the shift register in the lock detection circuit, which can avoid that when the shift register bits in the CDR lock detection circuit are few, the CDR has been locked, and the early The number of alternately appearing with late exceeds the threshold set by the CDR lock detection circuit, resulting in the situation that the CDR_LOCK signal cannot be stabilized at a high level. It can also solve the problem that when the shift register has a large number of digits, the output will be high regardless of whether the CDR is locked or not. The level problem improves the accuracy of the CDR lock detection circuit, and the PCS end can also obtain the correct CDR_LOCK indication signal.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design, in particular to a clock data recovery locking detection circuit adapting to variable bandwidth in high-speed serial communication. Background technique [0002] The clock and data recovery (CDR) circuit based on the phase interpolator (Phase Interpolator, PI) can track the frequency difference between the sending end and the receiving end very well, and has a large jitter tolerance, which is suitable for non-source synchronous occasions. It has been widely used in serial interface circuits. [0003] Whether the CDR circuit is locked can be judged by the oscilloscope based on the recovered clock and data "eyes", but the PCS end cannot know when the CDR can be locked, so a CDR lock detection circuit is needed to inform the PCS end whether the CDR circuit is locked or not. Already locked, when the CDR is locked, the PCS side can perform the next step on the recovered data and clo...

AI Technical Summary

Problems solved by technology

However, the circuit structure may appear that the CDR has been locked, and the CDR_LOCK signal still cannot be stabilized at a high level.

When there is a certain frequency difference between the sending end and the receiving end, the number of early and late alternately appearing may exceed the set threshold, but at this time the CDR is actually locked, but the clock jitter is relatively large. In this case The threshold for CDR lock detection needs to be raised under

However, if the threshold of CDR lock detection is increased blindly, it will result in the output of CDR_LOCK with a constant high level, and it is impossible to judge whether the CDR is locked.

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