Error positioning method and system based on RTL-level power consumption analysis

Abstract

The invention discloses an error positioning method and system based on RTL-level power consumption analysis. The error positioning method includes the steps that an executable tested design DUT, a reference design REF and a test case set are obtained; test cases sequentially run, and the tested design DUT and the reference design REF are subjected to power consumption evaluation respectively; power consumption of the tested design DUT and power consumption of the reference design REF under specific test excitation are obtained respectively, and power consumption results are compared and analyzed; according to the power-consumption comparison results, the designs are subjected to error positioning analysis of power consumption defects layer by layer from top to bottom; the accuracy of thepower consumption defects positioned in the tested design DUT is verified; a dislocation positioning report of the power consumption defects is fed back to designers. According to the error positioning method and system based on RTL-level power consumption analysis, limitation that functional errors in designs can be only positioned with the main verification technology can be overcome, the defects that in the physical design stage, power-consumption optimizing space is low, and the design iteration cycle is long can also be overcome, and the function that the power consumption defects are early positioned can be achieved in the logical design stage of a microprocessor.

Description

technical field [0001] The invention relates to the field of low power consumption verification of microprocessors, in particular to an error location method and system based on RTL-level power consumption analysis. Background technique [0002] As the core of various modern computer equipment, microprocessor chips lead the rapid development of integrated circuits and information technology in the industry. With the continuous development of semiconductor technology and the continuous improvement of chip performance requirements, the integration of chip systems is getting higher and higher, and the design of microprocessors is facing a series of problems and challenges. The sharply rising power consumption has become a crucial issue. . On the one hand, due to the heat dissipation and power noise caused by the power consumption of the microprocessor, it affects the packaging, testing and system reliability of the chip; on the other hand, due to the shortage of energy and the...

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Problems solved by technology

[0006] Technical problem to be solved by the present invention: Aiming at the above-mentioned problems of the prior art, an error location method and system based on RTL-level power consumption analysis is provided. The present invention can realize power consumption analysis and power consumption defects in the early stage of microprocessor chip design Processes such as positioning and verification greatly shorten the design iteration time, break through the limitations of mainstream verification technologies such as simulation verification, formal verification and other methods that cannot verify power consumption defects, and make up for the small space for power consumption optimization in the physical design stage and design iteration time Insufficient to meet the expected low-power design requirements and goals with faster speed and higher efficiency

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