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H2D write operation acceleration method and apparatus, compute device and storage medium

An acceleration device and storage medium technology, applied in computer equipment and storage media, H2D write operation acceleration method, device field, can solve the problems of low H2D write operation efficiency, high CPU overhead, low SSD read and write performance, etc., to reduce software The effect of hardware interaction, reducing coupling, and improving SSD write performance

Active Publication Date: 2018-12-07
SHENZHEN YILIAN INFORMATION SYST CO LTD
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Among them, 6 steps are pure software actions, 5 steps are software and hardware interactions, and only 2 steps are pure hardware actions. Due to the existence of many software actions, the CPU overhead is large; there are many software and hardware interactions, and there is time overhead. Often have to wait for the software trigger to start working, resulting in low efficiency of H2D write operations and low SSD read and write performance

Method used

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  • H2D write operation acceleration method and apparatus, compute device and storage medium
  • H2D write operation acceleration method and apparatus, compute device and storage medium
  • H2D write operation acceleration method and apparatus, compute device and storage medium

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Embodiment Construction

[0052] In order to fully understand the technical content of the present invention, the technical solutions of the present invention will be further introduced and illustrated below in conjunction with specific examples, but not limited thereto.

[0053] It should be understood that when used in this specification and the appended claims, the terms "comprising" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude one or Presence or addition of multiple other features, integers, steps, operations, elements, components and / or collections thereof.

[0054] It should also be understood that the terminology used in the specification of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this specification and the appended claims, the singular forms "a", "an" and "the" are intended to include plural referents unless th...

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Abstract

The invention relates to an H2D write operation acceleration method and apparatus, a computer device and a storage medium. The method includes the steps of designing an FIFO queue for storing a Flashaddress; obtaining an H2D write command of a host; analyzing and processing the H2D write command; moving the data into the buffer space of a memory; obtaining a preset Flash address to be written from a first in first out queue; writing data into a Flash address to be written; recycle buffer space for memory. As the FIFO array is arranged and the Flash address to be written obtain by an FTL algorithm is stored in advance, so when the hardware needs to write data with the Flash address to be written, the Flash address to be written is directly called without waiting for the FTL algorithm to provide the Flash address to be written in real time, thus simplifying the software operation steps, greatly reducing the CPU overhead, fully releasing the hardware performance, and improving the SSD writing performance.

Description

technical field [0001] The present invention relates to an H2D writing operation method, and more specifically refers to an H2D writing operation acceleration method, device, computer equipment, and storage medium. Background technique [0002] The existing H2D write command method is as follows figure 1 As shown, it includes: hardware obtains H2D write commands; firmware waits for commands (including query or interrupt mode); firmware parses commands; firmware applies for buffer space; firmware generates NVME PRD commands (ie non-volatile memory host controller interface specification PRD command) and send it to the NVME circuit for execution; the firmware FTL algorithm generates the Flash address to be written; the NVME circuit reads data from the host according to the PRD command and stores it in the buffer; the firmware waits for the data transmission to complete and the FTL algorithm generates the flash address to be written After entering the Flash address, generate a...

Claims

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Application Information

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IPC IPC(8): G06F12/02
CPCG06F12/0246
Inventor 余桉汤晓东钱鹏
Owner SHENZHEN YILIAN INFORMATION SYST CO LTD
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