SHA512 full-pipeline circuit based on on-chip memory and its implementation method

Abstract

The invention discloses an SHA512 fully-pipelined circuit based on an on-chip memory and an implementation method thereof. The SHA512 fully-pipelined circuit is provided with a message filling module,a Wt value generating module, a BRAM data storage module, a fully-pipelined hash operation module and an adder module, wherein the message filling module, the Wt value generating module, the BRAM data storage module, the fully-pipelined hash operation module and the adder module are connected in sequence. In a fully-pipelined architecture, an on-chip BRAM storage module is used for storing Wt values, and the whole circuit system consists of the message filling module, the Wt value generating module, the fully-pipelined hash operation module, the BRAM storage module and the adder module whichare connected in sequence. The throughput of an SHA-512 algorithm on an FPGA (Field Programmable Gate Array) is improved; the allocation of resources within the FPGA is balanced; and the efficiency ofthe algorithm is improved. The SHA512 fully-pipelined circuit has the characteristics of high throughput and high throughput per unit resource, and can be applied to the implementation of the SHA-512algorithm based on the FPGA.

Description

technical field [0001] The invention relates to the technical field of information security, in particular to a SHA512 full-pipeline circuit based on on-chip memory with high throughput rate, high unit resource throughput rate and high efficiency and its realization method. Background technique [0002] In the field of information security, the SHA-512 algorithm is often used to verify the integrity and accuracy of information, and is one of the hash functions widely used in security-related protocols and software. The SHA-512 algorithm accepts input information of any length less than 2 to the power of 128 bits, and generates a fixed 512-bit information digest output. SHA-512 is a one-way hash function and an irreversible string transformation algorithm, that is, it is impossible to reversely obtain the original information from a SHA-512 information digest. [0003] Field-Programmable Gate Array (Field-Programmable Gate Array, FPGA) is a program-driven programmable logic ...

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Problems solved by technology

In summary, the prior art does not relate to the implementation method of the SHA-512 algorithm full pipeline circuit based on the FPGA on-chip memory BRAM

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