PHY interface and FPGA chip based on FPGA primitive

Abstract

The invention discloses a PHY interface based on FPGA primitive. The PHY interface includes input and output buffers, a delay unit, an input serial-to-parallel converter and an output serial-to-parallel converter Both the input serial-to-parallel converter and the output serial-to-parallel converter are connected to a user logic block, the input serial-to-parallel converter and the output serial-to-parallel converter are both provided with an input interface clock and a frequency dividing clock, and the user logic module can adjust the phase difference between the input interface clock and thefrequency dividing clock to change the data transmission delay of the PHY interface. The inherent delay of the PHY interface realized by FPGA primitive is low and data transmission delay can be adjusted by adjusting clock of user logic module, flexibility of PHY interface is improved and data transmission delay of PHY interface is reduced. The invention also provides an FPGA chip, the function ofwhich corresponds to the PHY interface.

Description

technical field [0001] The invention relates to the FPGA field, in particular to a PHY interface and an FPGA chip based on FPGA primitives. Background technique [0002] PHY is the physical layer, and the PHY interface refers to the physical layer interface for data transmission between chip-to-chip or circuit board-to-circuit board. For example, in Ethernet applications, Ethernet data must pass through the PHY interface chip and then be transmitted to the CPU; on FPGA-based application platforms, FPGA control and data signals must pass through the high-speed PHY interface and then be transmitted to peripheral PCIe devices or DDR4 on the memory stick. In high-speed data applications, the PHY interface module (implemented by chips, application-specific integrated circuits or FPGA logic) is an essential part. The transmission speed and delay time of the PHY interface are important indicators to measure the interface. [0003] At present, there are dedicated PHY interface chi...

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a kind of PHY interface and FPGA chip based on FPGA primitive, in order to solve the problem that traditional PHY interface delay period is long, can not dynamically configure the delay parameter

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