Cellular neural network hardware architecture optimization method

A neural network and hardware architecture technology, applied in biological neural network models, physical implementation, etc., can solve the problems of redundant computing performance, slow memory reading, lack of reconfigurable design space exploration, etc., to achieve optimal computing performance, The effect of memory bandwidth reduction

CN108596331AInactive Publication Date: 2018-09-28ZHEJIANG UNIV
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Publication Date
2018-09-28
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention discloses a cellular neural network hardware architecture optimization method. The method comprises the steps of constructing cellular neural network hardware architecture and realizingsystem-level optimal design, module-level optimal design and design space-level optimal design for a calculation acceleration unit, wherein the architecture consists of an external memory, a memory interface controller, an on-chip input cache, an on-chip output cache, the calculation acceleration unit and a bus; the calculation acceleration unit comprises a plurality of iteration units which are connected in sequence; each iteration unit comprises a plurality of parallel operation modules; data is operated in the calculation acceleration unit and the operation result is written into the on-chip output cache; and an operation of the whole cellular neural network is completed through the iteration units in an assembly line manner. According to the method, parallel calculation of the cellularneural network is realized through system-level optimization, memory bandwidth in hardware is sufficiently utilized and data transmission delay is decreased through module-level optimization, and optimal calculation performance of systems is achieved under the condition of limited hardware resources through design space-level optimization.
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Description

technical field

[0001] The invention belongs to the field of hardware accelerator design, and in particular relates to an optimization method for cellular neural network hardware architecture. Background technique

[0002] With the increasing demand of artificial intelligence for low-power devices, the shortcomings of traditional image processing applications, such as low data processing speed and high power consumption, are becoming more and more obvious. As an effective means to improve processing performance and reduce energy consumption, cellular neural network has gradually been applied in the fields of noise elimination, edge detection, path planning, etc., and has attracted extensive attention from both academia and industry.

[0003] The cellular neural network is a nonlinear structure that is locally connected and composed of a large number of cells. Each cell has a template composed of a 3x3 matrix and is connected to its adjacent 8 cells. The parameters in the tem...

Examples

Embodiment Construction

[0043] The present invention will be further described below in conjunction with the accompanying drawings.

[0044] Such as figure 1 As shown, the cellular neural network hardware architecture is composed of external memory, memory interface controller, on-chip input cache, on-chip output cache, computing acceleration unit and AXI4 bus. Due to the limited on-chip storage resources, the data is first read from the external memory into the on-chip input buffer through the memory interface controller and the AXI4 bus, and the calculation operation is performed in the computing acceleration unit. The calculation acceleration unit includes a template RAM, a data transmission control unit, an iterative unit A and several iterative units B connected in sequence, and the operation of the entire cellular neural network is completed through the iterative unit pipeline. The details are as follows:

[0045] Iteration unit A (IU A): perform the initial calculation operation in the iterativ...