Cellular neural network hardware architecture optimization method

Abstract

The invention discloses a cellular neural network hardware architecture optimization method. The method comprises the steps of constructing cellular neural network hardware architecture and realizingsystem-level optimal design, module-level optimal design and design space-level optimal design for a calculation acceleration unit, wherein the architecture consists of an external memory, a memory interface controller, an on-chip input cache, an on-chip output cache, the calculation acceleration unit and a bus; the calculation acceleration unit comprises a plurality of iteration units which are connected in sequence; each iteration unit comprises a plurality of parallel operation modules; data is operated in the calculation acceleration unit and the operation result is written into the on-chip output cache; and an operation of the whole cellular neural network is completed through the iteration units in an assembly line manner. According to the method, parallel calculation of the cellularneural network is realized through system-level optimization, memory bandwidth in hardware is sufficiently utilized and data transmission delay is decreased through module-level optimization, and optimal calculation performance of systems is achieved under the condition of limited hardware resources through design space-level optimization.

Description

technical field [0001] The invention belongs to the field of hardware accelerator design, and in particular relates to an optimization method for cellular neural network hardware architecture. Background technique [0002] With the increasing demand of artificial intelligence for low-power devices, the shortcomings of traditional image processing applications, such as low data processing speed and high power consumption, are becoming more and more obvious. As an effective means to improve processing performance and reduce energy consumption, cellular neural network has gradually been applied in the fields of noise elimination, edge detection, path planning, etc., and has attracted extensive attention from both academia and industry. [0003] The cellular neural network is a nonlinear structure that is locally connected and composed of a large number of cells. Each cell has a template composed of a 3x3 matrix and is connected to its adjacent 8 cells. The parameters in the tem...

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Problems solved by technology

[0012] 1. The iterative operation of most of the existing cellular neural network hardware designs is only executed in one operation module, which does not make full use of the parallel features of the hardware

[0013] 2. The current work does not take into account that repeated reading and writing parameters in the neural network will cause unnecessary memory bandwidth and storage resource occupation, and make use of this feature

Because the memory read in FPGA is much slower than the calculation speed, these repeated parameters will cause calculation performance redundancy

[0014] 3. Many cellular neural network systems do not make full use of hardware resources and bandwidth. This lack of reconfigurable design space exploration makes it difficult for hardware to achieve optimal performance

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