Floating base substrate for chip semiconductor testing

A semiconductor and pedestal technology, applied in the field of floating pedestal substrates for chip semiconductor testing, can solve problems such as delays, inability to really solve virtual solder damage, and affect the quality of chip units.

Active Publication Date: 2018-12-14
INTEL PROD CHENGDU CO LTD +1
View PDF8 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in this type of testing method in the prior art, there will be a certain delay from the test to the back-track inspection, that is, only when the downstream chip unit reaches the back-track step of the test, the defective chip unit can be detected, so that there will be Conditions that have affected the quality of hundreds of thousands of chip units
[0005] Therefore, it can be seen that the traditional solution only minimizes the scope of influence of virtual welding, but cannot really solve the damage caused by virtual welding

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Floating base substrate for chip semiconductor testing
  • Floating base substrate for chip semiconductor testing
  • Floating base substrate for chip semiconductor testing

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0069] Example 1: For Product A

[0070]

[0071] Conclusion: For product A whose original design does not meet design criterion 1 or design criterion 2, the defect of virtual soldering will cause continuous damage to the subsequent test product, and the damage will reach the scrapping standard of visual inspection after packaging. False soldering defects will damage all the good products in the follow-up test and the damage will reach the scrapping standard, which will have a considerable impact on the yield rate; according to the characteristics of the product and various boundary conditions allowed by the test hardware (R to bo s <=450μm) use the inventive model to calculate the optimal solution as shown in the table. The original design has a 100% impact on the yield rate in the case of false welding defects, that is, all subsequent test products will be damaged and the damage reaches the scrap standard; the improved design is actually used in the case of false welding ...

Embodiment 2

[0072] Example 2: For Product B

[0073]

[0074] Conclusion: For product B whose original design does not meet design criterion 1 or design criterion 2, the defect of solder joints will cause continuous damage to the subsequent test product, and the damage will reach the scrapping standard of visual inspection after packaging. False soldering defects will damage all the good products in the follow-up test and the damage will reach the scrap standard, which will have a considerable impact on the yield rate; according to the characteristics of the product and various boundary conditions allowed by the test hardware (R to bo s bo and H s Do proper optimization. The original design has a 100% impact on the yield rate in the case of false welding defects, that is, all subsequent test products will be damaged and the damage reaches the scrap standard; the improved design is actually used in the case of false welding defects, and it is found that its The resulting yield impact ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a floating base substrate and method for chip semiconductor testing. The floating base substrate at least comprises a substrate provided with at least one same detection cavity, wherein the radius of the upper opening of each detection cavity is greater than the radius of the lower opening, a welding ball used for accommodating to-be-detected products, at least one test probe fixed to the base and adopting an elastic telescopic rod structure, wherein the tops of the test probes can extend into the detection cavity and can move up and down, and the base can be driven tomove up and down by the test probes. Power testing can be conducted by test probe being contact with welding ball. When the detected welding ball falling off caused by virtual welding defect is extruded and deformed, sequential testing is conducted, and whether the welding ball is normal is judged according to the damage surface. The structural model is based on spherical contact array package andvirtual welding. The damage risk of the welding ball is determined by calculating spherical contact array package parameters and mechanical interference of the design size of floating base.

Description

technical field [0001] The invention relates to a testing technology of a semiconductor chip, in particular to a floating base substrate and a method for chip semiconductor testing. Background technique [0002] Wet soldering is a common failure condition for ball contact array packages. As shown in Figure 1, in this case, since the ball of the solder ball does not form a metal bond under the action of the substrate, it will fall off under the action of mechanical external force during the test. The dislodged solder balls will get stuck on the floating pedestal, and there are instances during testing of ball contact array packages with subsequent damage not detected. The above test process includes PPV test, and electrical performance test. [0003] In a large-scale mass production environment, it is difficult to completely eliminate the problem of virtual soldering of the ball contact array, and the traditional assembly and testing process can only detect the problem thro...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): G01R1/073
Inventor 周凡骆毅高薇邓杨琨谭伟
Owner INTEL PROD CHENGDU CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap