Scheduler for out-of-order block isa processors

Abstract

Apparatus and methods are disclosed for implementing incremental schedulers for out-of-order block-based processors, including field programmable gate array implementations. In one example of the disclosed technology, a processor includes an instruction scheduler formed by configuring one or more look up table RAMs to store ready state data for a plurality of instructions in an instruction block.The instruction scheduler further includes a plurality of queues that store ready state data for the processor and sends dependency information to ready determination logic on a first in / first out basis. The instruction scheduler selects one or more of the ready instructions to be issued and executed by the block-based processor.

Description

Background technique [0001] Due to the continued transistor scaling predicted by Moore's Law, microprocessors have benefited from continued increases in transistor count, integrated circuit cost, manufacturing capital, clock frequency, and energy efficiency, while the associated processor instruction set The architecture (ISA) has changed very little. However, the benefits realized from the lithographic scaling that has driven the semiconductor industry for the past 40 years are slowing or even reversing. The Reduced Instruction Set Computing (RISC) architecture has been the dominant paradigm in processor design for many years. Out-of-order superscalar implementations have not shown consistent improvements in area or performance. Therefore, there is ample opportunity for improvements in processor ISAs to scale performance improvements. Contents of the invention [0002] Methods, apparatus, and computer-readable storage devices for configuring, manipulating, and compiling ...

AI Technical Summary

Problems solved by technology

Out-of-order superscalar implementations have not shown consistent improvements in area or performance

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