Data latch circuit, page data latch and method for flash memory page programming

Abstract

The invention discloses a data latch circuit for flash memory page programming, a page data latch and a method thereof. The data latch circuit comprises a data input circuit and n groups of main latchcircuits connected with the data input circuit. The data input circuit includes a fifth transistor, a sixth transistor and a seventh transistor. The gate of the fifth transistor and the gate of the sixth transistor are inversely connected in series with the input pb_b signal. The source of the sixth transistor serves as an input terminal of the data Din; the source of the fifth transistor servesas an input terminal of the inverting data Dinb of the data Din; the gate of the seventh transistor inputs an inverted eq signal for balancing the drain voltages of the fifth transistor and the sixthtransistor to prevent crosstalk during data writing; the drains of the fifth transistor and the seventh transistor are connected to the inputs a of each main latch circuit. The drain of the sixth transistor and the source of the seventh transistor are connected to the inputs b of the respective main latch circuits. The invention has the advantages of increasing driving capacity and saving circuitarea.

Description

technical field [0001] The invention relates to the field of memory, in particular to a data latch circuit for flash page programming, a page data latch and a method. Background technique [0002] In the flash memory based on the SONOS process, each bit line needs to correspond to a set of data latches, and the data in all the latches are simultaneously written into the memory array during page programming. In the flash memory, a large number of data latches are required, while traditional data latches have a large number of devices, a large size, and a large circuit area. A flash memory generally includes 1024 page data latches of the main latch circuit, or even more. [0003] Conventional data latches such as figure 1 As shown, the data Din and Dinb (Dinb is the inverse of Din) are added to the gates of P6 and P7. pa_b and pb_b select data latches through P2, P3, P4, and P5 respectively. Since P2, P4, and P6 are connected in series, the drive capacity is small, so a la...

AI Technical Summary

Problems solved by technology

Since P2, P4, and P6 are connected in series, the drive capacity is small, so a larger size is required

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