Low-dropout linear voltage stabilizer based on self-adaptive zero compensation
A low-dropout linear and zero-point compensation technology, which is applied to instruments, electrical variable adjustment, control/regulation systems, etc., to achieve the effect of improving loop stability and maintaining loop stability
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[0027] [Example 1]
[0028] The present invention proposes a low-dropout linear regulator based on adaptive zero compensation, such as figure 2 As shown, it includes a reference voltage circuit, an error amplifier, a series regulator MPO, and a feedback network composed of a first resistor R1 and a second resistor R2. The inverting input of the error amplifier is connected to the reference voltage circuit, and the non-inverting input is connected to the first resistor. One end of a resistor R1 and one end of a second resistor R2, the output end of which is connected to the gate end of the series regulator MPO, the source end of the series regulator MPO is connected to the power supply VIN, and the drain end of the series regulator MPO is connected to the stable The other end of the first resistor R1 is connected to the drain end of the series regulator MPO, and the other end of the second resistor R2 is grounded.
[0029] Please continue to refer figure 2 , The low-dropout linear...
Example Embodiment
[0043] [Example 2]
[0044] The embodiment of the present invention provides a technical solution: the difference from embodiment 1 is that Figure 4 The adaptive compensation control circuit includes a fourth PMOS tube MP4, a fifth PMOS tube MP5, a third NMOS tube MN3, and a resistor R0. The drain terminal and the gate terminal of the fourth PMOS tube MP4 are connected to and connected to the The drain terminal of the third NMOS tube MN3 is connected, the gate terminal of the fifth PMOS tube MP5 is connected with the gate terminal of the fourth PMOS tube MP4, and the drain terminal is connected to one end of the resistor R0 and the second NMOS tube respectively. The drain terminal of the tube MN2 is connected to the gate terminal of the first PMOS tube MP1, the other end of the resistor R0 is grounded, and the source terminals of the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are connected to the power supply , The source terminal of the third NMOS transistor MN3 is ground...
Example Embodiment
[0047] [Example 3]
[0048] The embodiment of the present invention provides a technical solution: the difference from embodiment 1 is that for the case of VOUT=VREF in embodiment 1, it can be seen that R1=0, that is, no resistor R1 is required, only one resistor R2 is required, but further , Taking into account the actual cost and process requirements of the resistor, in the embodiment of the present invention, such as Figure 5 As shown, an NMOS tube MN0 is used to replace the second resistor R2. The low dropout linear regulator also includes a bias circuit and an NMOS tube MN0 that can be used as an output load. The bias circuit includes a bias current source IB, a fourth NMOS tube MN4, and the bias current source IB The input terminal is connected to the power supply, the output terminal is connected to the drain terminal of the fourth NMOS tube MN4, the drain terminal of the fourth NMOS tube MN4 is connected to the gate terminal, and the source terminal is grounded. The gate...
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