A Design Method for Embedded Core Test Package Scan Chain

A technology for testing packaging and design methods, applied in the field of on-chip systems, can solve problems such as defects and serious faults, and achieve the effects of shortening test time, improving balance results, and increasing population diversity

Active Publication Date: 2021-08-27
GUILIN UNIV OF ELECTRONIC TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as the density of embedded cores increases, defects and failures in SoC become more serious

Method used

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  • A Design Method for Embedded Core Test Package Scan Chain
  • A Design Method for Embedded Core Test Package Scan Chain
  • A Design Method for Embedded Core Test Package Scan Chain

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Embodiment Construction

[0032] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, in the case of no conflict, the following embodiments and features in the embodiments can be combined with each other.

[0033] It should be noted that the diagrams provided in the following embodiments are only schematically illustrating the basic ideas of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the compo...

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Abstract

The present invention proposes a kind of embedded core test packaging scan chain design method, including step (1): algorithm initialization; step (2): de-initialization step (3): if the end condition is not satisfied, continue, otherwise go to step (12 ); Step (4): Estimate the objective function max(s i ,s o ) value; step (5): adjust food sources and enemies; step (6): adjust individual separation S, individual direction A, individual cohesion C, individual food F, position D and weight of individual enemies w; Step (7): Evaluate S, A, C, F, and D; Step (8): Adjust the neighborhood radius; Step (9): Adjust the location vector; Step (10): Validate according to the bounds of the variables and Modify the new position, if the value of the new position is less than 1, set its value to 1, if it is greater than N, then set its value to N; step (11): go to step (3); step (12): Output the result.

Description

technical field [0001] The invention relates to the field of a system on chip (System-on-Chip, SoC), in particular to a design method for an embedded core test package scan chain. Background technique [0002] Today, advanced silicon chip manufacturing makes it possible to integrate more transistors, which allows hundreds of embedded cores with various structures including random access memory (RAM), read-only memory (ROM) on a single chip , digital signal processor (DSP), combinational logic block (CLB) and central processing unit (CPU), etc. This pattern becomes essential in SoC design as the reuse of pre-designed and pre-verified embedded cores significantly reduces the overall design cycle and cost. However, as the density of embedded cores increases, defects and failures in SoCs become more severe. Therefore, the verification and testing of embedded cores is of great significance to a successful SoC design. Test development is also recommended to be core-based to avo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/3185
CPCG01R31/318583
Inventor 周甜胡聪朱望纯朱爱军许川佩陈涛
Owner GUILIN UNIV OF ELECTRONIC TECH
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