Test device for memory device and related test and manufacturing method for memory device

Abstract

Embodiments of the present invention disclose a memory test system including a memory integrated circuit (IC) and a memory function tester. The memory IC includes a plurality of memory banks, wherein each memory bank includes a plurality of memory cells. The memory functional tester includes an adjustable voltage generator circuit, a read current measurement circuit, and a controller. The memory functional tester performs a write / read functional test on the memory bank with a plurality of write control voltages to determine the preferred write control voltage, wherein the preferred write control voltage is specified in the memory bank during the operating mode Used during subsequent write operations. Embodiments of the present invention also provide methods of fabricating and testing memory devices having multiple memory banks.

Description

technical field [0001] Embodiments of the present invention generally relate to the field of electronic circuits, and more particularly, relate to a memory function tester and related memory manufacturing and testing methods. Background technique [0002] Data storage devices are electronic devices used to write and / or read electronic data. Data storage devices can be implemented as volatile memory, such as random access memory (RAM), which typically requires power to maintain its stored information, or as nonvolatile memory, which can maintain its stored information even when power is removed (such as read-only memory (ROM)). RAM can be implemented in configurations of dynamic random access memory (DRAM), static random access memory (SRAM), and / or non-volatile random access memory (NVRAM), commonly referred to as flash memory. Electronic data may be written to and / or read from the array of memory cells accessible through various control lines. [0003] Magnetoresistive R...

AI Technical Summary

Problems solved by technology

Different die at different wafer locations (e.g. center die vs. edge die) and different blocks of a single large MRAM or RRAMIC can often have wildly different read / write windows, and with very high probability cannot Performance testing with read / write window margins, which can limit the usefulness of MRAM and RRAM devices

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