Low-latency ARINC 818 bus transceiving method

Abstract

The invention proposes a low-latency ARINC 818 bus transceiving method. During the realization of mutual conversion between a VESA protocol and an ARINC 818 protocol according to the FPGA, the bufferamount of the data at a transmitting end can be reduced from the current frame to 1 line, and the buffer amount of the data at a receiving end can be reduced from the current frame to 40 lines due tothe optimization of a control algorithm, which greatly improves the real-time performance of video transmission. At the same time, resources required by the caching of a new algorithm can be satisfiedby the internal resources of the FPGA with no external memory needed, which reduces the difficulty of hardware design, reduces the resource overhead, and reduces the power consumption.

Description

technical field [0001] The invention relates to the field of aviation bus, in particular to an FPGA-based ARINC818 transceiver method with no external storage, less cache, and low delay. Background technique [0002] In recent years, in the field of aviation buses, the amount of data transmitted is increasing, and the requirements for data delay performance are also getting higher and higher. The transmission rate of traditional digital aviation bus, such as ARINC429, can no longer meet the demand. On this basis, the ARINC818 bus protocol formulated according to the FC-AV protocol has become a new generation of aviation video bus protocol, and it is used in Airbus and Boeing It has been well applied on various models. [0003] The domestic research on the ARINC818 bus started relatively late. The current design basically uses FPGA to realize the protocol conversion and transmission of video data, and the currently used protocol conversion algorithm and process need to buffe...

AI Technical Summary

Problems solved by technology

This brings about a large video transmission delay. At the same time, due to the large amount of video from one to two frames, the internal resources of the FPGA cannot meet the cache requirements, and an external memory is required to meet the design, which increases the system size. The difficulty of design increases the overhead of hardware, and the power consumption of the whole system will increase accordingly

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