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Control method, device, electronic equipment and storage medium of digital time converter

A technology of digital time and control method, applied in the direction of time-to-digital converter, device for measuring time interval, electrical unknown time interval measurement, etc., which can solve problems such as large nonlinearity and mismatch of circuit components

Active Publication Date: 2019-02-19
PEKING UNIV SHENZHEN GRADUATE SCHOOL
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the mismatch problem of the circuit components themselves, controlling the capacitance through a continuously changing multi-bit binary control signal will introduce a very large nonlinearity.

Method used

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  • Control method, device, electronic equipment and storage medium of digital time converter
  • Control method, device, electronic equipment and storage medium of digital time converter
  • Control method, device, electronic equipment and storage medium of digital time converter

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Embodiment Construction

[0049] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0050] The network architecture to which the solutions of the embodiments of the present application may be applied is firstly described below with reference to related drawings.

[0051] Wherein, the above-mentioned network architecture can be specifically applied to digital circuits, such as digital time converters, all-digital phase-locked loops, clock and data recovery circuits, and the like. Taking the digital time converter as an example here, th...

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PUM

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Abstract

The embodiment of the invention provides a control method, a device, an electronic equipment and a storage medium of a digital time converter, the method comprises the steps of: obtaining input control information, which comprises multiple pieces of subcontrol information; converting the control information into coordinate information of a capacitor; acquiring capacitance information of corresponding coordinates based on the coordinate information, wherein the capacitance information comprises capacitance values; obtaining total capacitance information according to the capacitance information, wherein the total capacitance information comprises a total capacitance value; and responding according to the total capacitance information. According to the control method, the device, the electronic equipment and the storage medium of digital time converter, nonlinearity of a digital circuit which uses binary control information only to control the capacitor can be reduced since the binary control information portion is converted to thermometer coded information.

Description

technical field [0001] The present invention relates to the technical field of digital circuits, in particular to a digital time converter control method, device, electronic equipment and storage medium. Background technique [0002] At present, digital circuit modules such as all-digital phase-locked loops (ADPLL), clock and data recovery (CDR) and direct phase modulators in polar or out-of-phase transmitters are often used in the field of digital circuits, while digital time converters ( DTC) plays a key role in these blocks, and the phase error of DTC affects the spectrum and error vector magnitude of the transmitter as well as the phase error of the ADPLL and CDR circuits. Therefore, DTC with high resolution and high linearity has been a research hotspot at home and abroad. For example, the main cause of ADPLL's fractional spurs is the non-linearity of DTC, so a high linearity DTC can effectively reduce ADPLL's fractional spurs. [0003] At present, if DTC is used to a...

Claims

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Application Information

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IPC IPC(8): G04F10/00
CPCG04F10/005
Inventor 王俊瑶汪波王新安王海锐许郁冰陈红英何春舅
Owner PEKING UNIV SHENZHEN GRADUATE SCHOOL
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