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A system for multiplying matrix vectors and a method for performing neural network operations

A multiplication, matrix-vector technology, applied in the system field of matrix-vector multiplication, which can solve the problems of data processing speed limit, energy and hardware resource consumption sharply increased, etc.

Inactive Publication Date: 2019-02-19
PEKING UNIV
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  • Application Information

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Problems solved by technology

[0002] The development of deep learning and artificial intelligence puts forward strict requirements on the energy efficiency ratio and hardware consumption of data processing. The traditional von Neumann-based computing architecture is limited by the central processing unit CPU and The bottleneck of data transmission between memories, the speed of data processing is greatly limited, and the consumption of energy and hardware resources increases sharply

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  • A system for multiplying matrix vectors and a method for performing neural network operations
  • A system for multiplying matrix vectors and a method for performing neural network operations
  • A system for multiplying matrix vectors and a method for performing neural network operations

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[0037] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0038] According to the basic idea of ​​the present invention, the deep learning network includes convolution, pooling and fully connected layers. Essentially, matrix-vector multiplication operations occupy a large proportion in each layer. The integrated NOR FLASH storage and computing array can efficiently perform matrix-vector multiplication and accelerate deep learning. Specifically: the threshold voltage of the NOR FLASH unit can be adjusted by programming / erasing. When programming the NOR FLASH unit, hot electrons are injected, the threshold voltage of the device rises, and the storage state is regarded as "0"; when the NOR FLASH unit is programmed When erasing, electrons tunnel, the threshold voltage of the device ...

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Abstract

A system for multiplying matrix vectors comprises a NOR FLASH calculation array, wherein the gates of each column of cells in the array are connected together, and each column is used for sequentiallyinputting input voltages corresponding to elements of a multiplier vector; The drains of each row of cells in the array are connected together, and are used for outputting the operation current obtained by multiplying each cell and accumulating (i.e. Matrix vector multiplication). Each pair of behaviors in the array is a group, in which one row represents a negative number and the other a positive number, and each group is written in advance into the elements of the multiplier vector in a positive-negative relationship; A weighted summing circuit that performs weighted summing operations on the operation currents located in the same group representing different bits; A subtraction circuit is arrange in each group, and is used for subtract that weighted summation operation result representing different bits; An analog-to-digital conversion circuit for converting the result of the subtraction operation into a binary digit amount. Through the system of the invention, the integration of storage and calculation is realized.

Description

technical field [0001] The invention belongs to the field of semiconductor devices and integrated circuits, in particular to a system and method for performing matrix-vector multiplication operations based on a NORFLASH calculation array. Background technique [0002] The development of deep learning and artificial intelligence puts forward strict requirements on the energy efficiency ratio and hardware consumption of data processing. The traditional von Neumann-based computing architecture is limited by the central processing unit CPU and The bottleneck of data transmission between memories, the speed of data processing is greatly limited, and the consumption of energy and hardware resources increases sharply. There are a large number of matrix-vector multiplication operations in deep learning. The storage and computing integrated array designed based on NOR FLASH can perform matrix-vector multiplication operations in parallel, accelerate operations at the hardware level, a...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/16G06N3/063
CPCG06F17/16G06N3/063
Inventor 康晋锋项亚臣黄鹏韩润泽刘晓彦
Owner PEKING UNIV