Driving circuit for neutral point clamped (NPC) three-level topology and application

Abstract

The invention discloses a driving circuit for a neutral point clamped (NPC) three-level topology and application. The driving circuit comprises a wave sealing time sequence protection circuit and a logic interlocking circuit which are sequentially connected, wherein the wave sealing time sequence protection circuit comprises a logic AND gate, the situation that a PWM pulse sequence of a second tube is a low level and a PWM pulse sequence of a first tube is also a low level by the logic AND gate, and / or a PWM pulse sequence of a third tube is a low level and a PWM pulse sequence of a fourth tube is also a low level, the logic interlocking circuit comprises a driving photocouple, an input signal of the driving photocouple is a PWM pulse sequence output from the wave sealing time sequence protection circuit, and complementary conduction of the first tube and the third tube and / or complementary conduction of the second tube and the fourth tube is achieved by the driving photocouple. By thedriving circuit, all pulse sequences of the control chip are low levels during power-on period, a complementary tube confirms to a reliable logic complementary relation, the cutoff time sequence requirement during wave sealing is met, and the switch tube is prevented from bearing overvoltage during overcurrent cutoff.

Description

technical field [0001] The invention belongs to the technical field of power electronics, and in particular relates to a drive circuit with a logic protection function for a diode-clamped NPC (NPC-Neutral Point Clamped) three-level topology drive circuit and its application. Background technique [0002] Diode-clamped three-level topology such as figure 1 As shown, its output has three levels, namely 0. refer to figure 1 , The sequence numbers of the switch tubes are defined as ① tube, ② tube, ③ tube and ④ tube from top to bottom. Its trigger pulse timing is as follows figure 2 As shown, tube ① and tube ③ are complementary, and tube ② and tube ④ are complementary; in the positive half cycle of the sine wave, tube ② remains on, tube ① and tube ③ are complementary, and in the negative half cycle of the sine wave, tube ③ Keep conducting, and the ② tube and the ④ tube are complementary to conduct. [0003] The driving circuit design of this topology has the following req...

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Problems solved by technology

[0004] In order to meet the requirements of the above logical relationship, the above rules must be added in the software design, but due to the pulse delay of the drive circuit itself and the influence of the parasitic parameters of the switching device itself, there is a phenomenon of control failure

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