Method for realizing parallel CRC by multi-stage pipeline circuit

Abstract

Provided is a method for realizing parallel CRC by a multi-stage pipeline circuit. 16-byte data input in each clock cycle is divided into a first 8-byte data block and a second 8-byte data block; thefirst 8-byte and the second 8-byte in each clock cycle respectively calculates a CRC32 result of the 8-bytes through a CRC32 module; a 8-byte shifting calculation module performs 64-time iterative shifting on the calculation result of the first 8-byte through the CRC32 module; an XOR operation is performed on a result of the 64-time iterative shifting and the direct 8-byte CRC32 calculation to obtain a 16-byte CRC32 result in a first clock cycle; and a 16-byte shifting calculation module performs 128-time iterative shifting on the 16-byte CRC32 result in the first clock cycle, the XOR operation is performed on the 16-byte CRC32 result in each clock cycle and the 16-byte CRC32 result in a previous clock cycle through a result after 128-time iterative shifting, and a final CRC32 result of acurrent clock cycle is obtained. A feedback circuit of an LFSR is removed so that multi-stage pipeline can be inserted, and the system data throughput is increased.

Description

technical field [0001] The invention relates to the technical field of electronic information, in particular to a method for realizing parallel CRC by a multi-stage pipeline circuit. Background technique [0002] At present, the CRC algorithm has been widely used in the communication field as a way of data protection. The CRC algorithm is generally implemented by LFSR on the hardware circuit. There are two methods: serial and parallel. However, there is a feedback loop in the circuit structure of LFSR, and it is impossible to increase the operating frequency by inserting multi-stage pipelines, especially when using parallel methods. When the CRC algorithm is implemented and the data bit width is large, the combinational logic can reach more than 30 levels. Since the combinational logic cannot be inserted into the pipeline, the operating frequency of the circuit cannot be effectively increased. Contents of the invention [0003] (1) Solved technical problems [0004] Aimi...

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Problems solved by technology

[0004] Aiming at the deficiencies of the prior art, the present invention provides a method for realizing parallel CRC in a multi-stage pipeline circuit, which has the advantages of being able to insert multi-level pipeline segmentation combination logic, increasing the operating frequency of the circuit, and achieving the goal of increasing the system throughput rate. Solved the problem that the existing CRC algorithm using LFSR circuit cannot be inserted into multi-stage pipeline and thus cannot increase the operating frequency of the circuit

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