Parallel test method for semiconductor power devices

Abstract

The invention discloses a parallel test method for semiconductor power devices. The parallel test method is used for performing parallel tests on the semiconductor power devices of the whole lead frame through a chip package test apparatus in a package test process, the chip package test apparatus comprises a test head (100) ), a test bracket (110) and an operating machine platform (111). The parallel test method comprises the following steps of step S1, precutting a rib; step S2, fixing a chip; step S3, arranging probes and establishing a loop; step S4, grouping the devices; and step S5, performing parallel tests. A switch control bit of a switch control module (108) controls the semiconductor power devices on a group A test station to perform parallel test according to a ping-pong test mode; after the group A test is completed, the switch control bit of the switch control module (108) controls the semiconductor power devices on a group B test station to perform parallel test according to the ping-pong test mode. With the parallel test method for the semiconductor power devices, the technical effect of improving the test efficiency is achieved.

Description

technical field [0001] The invention relates to the technical field (H01L 21 / 66) of testing or measuring methods or equipment specially adapted for use in the manufacture or processing of semiconductor or solid state devices or parts thereof, and in particular the invention relates to parallel testing methods for semiconductor power devices. Background technique [0002] The existing traditional production process of semiconductor power devices is as follows: figure 1 Shown: [0003] The wafer is pasted on the blue film at the wafer loading station, and the entire wafer is cut into individual chips by the wafer cutting station. The pad-type solder joints on the chip are then welded and connected to the designated lead pins on the frame with high-purity metal wires at the chip bonding station, and then the overall thermal hardening and injection molding are cured, and the chip after electroplating pins are trimmed and formed Put it in the tube and then segregate and test th...

AI Technical Summary

Problems solved by technology

[0005] (1) The test speed of a single chip is slow, and the cumulative production cycle of chip transfer time is long

[0006] (2) The individual factors of a single chip lead to an increase in the quality risk of human interference factors

[0007] (3) Each single-chip general-purpose gold finger needs to be positioned separately, which will easily lead to a drop in the test yield rate caused by poor contact, resulting in unnecessary cost waste

[0022] Patent document CN103311143B discloses a chip package testing device and the lead frame used therein, but does not disclose the specific structural design of the parallel testing device

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