FPGA implementation method suitable for pulse compression of large pulse width signal

Abstract

The invention provides an FPGA implementation method suitable for pulse compression of a large pulse width signal. The method comprises the following steps of (S1) transmitting a pulse echo signal collected after the down-conversion to a FFT module for FFT processing to obtain a two-channel frequency domain signal; (S2) conjugating and multiplying the obtained two-channel frequency domain signal by samples stored in the ROM in an FPGA chip; (S3) converting the multiplied result to a two-channel time domain signal by IFFT, and combining the two-channel time domain signal into one channel to complete the frequency domain pulse compression. The method reduces the problem of the requirement of hardware resources when the large pulse width signal is compressed, and achieves the pulse compression function of the large pulse width signal in the FPGA. The method has strong flexibility and has a strong practical value and a promotion value.

Description

technical field [0001] The invention relates to the technical field of radar signal processing, in particular to an FPGA implementation method suitable for pulse compression of large pulse width signals. Background technique [0002] Since the late 1950s, with the rapid development of flight technology, aircraft, missiles, satellites and other flight equipment have adopted radar as one of the methods of control and detection. In terms of performance, more and more strict requirements are put forward. According to the theory of radar signal processing, in ordinary pulse radar, there is an irreconcilable contradiction between the operating range and the range resolution. [0003] Pulse compression has become an important technology because it can solve the contradiction between target detection range and distance-resolution. Pulse compression technology is a good practical application of matched filtering theory and correlation receiving theory. Its proposal is very A good so...

AI Technical Summary

Problems solved by technology

The hardware implementation of pulse compression technology has probably gone through several stages, from analog pulse compression to digital pulse compression with DSP devices as the core, and then to digital pulse compression with field programmable gate array FPGA devices as the core. The analog pulse compression factor It has the disadvantages of poor anti-interference ability and inflexible control mode, but it has been replaced by digital pulse compression. The pulse compression scheme with DSP devices as the core has also been gradually adopted due to the shortcomings of low efficiency, slow speed, and large delay in implementing digital signal algorithms. It is replaced by the pulse compression scheme with FPGA as the core. FPGA is a digital integrated circuit device that can be programmed by users to realize the required logic functions. , the emergence of FPGA is only to replace traditional digital logic circuits, but as it is easy to achieve parallel computing and other excellent performance, it has gradually become a development trend to use FPGA to implement various signal processing algorithms

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