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Clock synchronization device suitable for auxiliary retap

A clock synchronization and splitter technology, applied in synchronization devices, digital transmission systems, electrical components, etc., can solve problems such as poor configuration flexibility, clock out-of-sync, no protection, etc., to achieve good consistency, solve out-of-sync, avoid effect of temperature

Active Publication Date: 2019-03-26
NO 54 INST OF CHINA ELECTRONICS SCI & TECH GRP
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Problems solved by technology

However, this method requires additional hardware circuits; and the frequency of the local voltage-controlled crystal oscillator is required to be an integer multiple of the input data clock. When the service rate changes or needs to support multiple service rates, it is necessary to change or configure multiple hardware locks at the same time. The configuration flexibility of the phase loop circuit and multiple voltage-controlled oscillators with different frequencies is poor; the hardware circuit has no protection measures for the input clock and data. The clock is out of sync, resulting in bit errors

Method used

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  • Clock synchronization device suitable for auxiliary retap

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Embodiment Construction

[0014] refer to figure 1 , the present invention consists of a clock shaping module 1, a second-order phase-locked loop circuit 2, a clock adjustment module 3, a sampling module 4 and a buffer module 5; figure 1 It is an electrical principle block diagram of the present invention, and the embodiment is according to figure 1 Connect the lines. At the sending end, the clock synchronization processing flow is implemented on the modem: the input of the clock shaping module 1 is the local clock generated by the local crystal oscillator and the data clock sent to the modem by the auxiliary multiplexer. In this module, the local clock is used to synchronize the data clock Perform buffering, sampling and shaping to obtain the rising edge in the data, and output the rising edge signal to the second-order phase-locked loop circuit 2 and the clock adjustment module 3 respectively; the second-order phase-locked loop circuit 2 uses the local clock as the processing clock, The rising edge...

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Abstract

The invention discloses a clock synchronization device suitable for auxiliary retaps, and relates to a scattering communication system adopting an auxiliary retap. Clock synchronization between the auxiliary retap and a modem is realized by adopting a full-software signal processing method, thereby simplifying a time synchronization hardware circuit and realizing higher reliability, more flexibleconfigurability and expandability. The clock synchronization device also adopts a method combining the clock synchronization and the data information buffer adjustment, thereby enhancing the clock jitter resistance of the system and improving the performance of the device.

Description

technical field [0001] The invention relates to a clock synchronization device suitable for auxiliary multiplexers in the communication field, and is especially suitable for solving the problem of complex hardware circuit and poor configuration flexibility of the time synchronization circuit between the auxiliary multiplexer and the modem in the scattering communication equipment. Lack of protection measures, easy to lose synchronization. Background technique [0002] The clock synchronization between the auxiliary multiplexer and the modem of the existing scattered communication equipment usually uses a digital device to build a phase-locked loop circuit. By controlling the local voltage-controlled oscillator and adjusting the local clock frequency, the local clock and the input data clock are achieved. Synchronize. However, this method requires additional hardware circuits; and the frequency of the local voltage-controlled crystal oscillator is required to be an integer m...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L7/033H04L7/00
CPCH04L7/0087H04L7/0331
Inventor 毛晶晶全亮李志勇陈小溪韩燕杰
Owner NO 54 INST OF CHINA ELECTRONICS SCI & TECH GRP
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