Circuits and methods providing electronic band gap (EBG) structures at memory module electrical coupling

Abstract

A system includes: a printed circuit board having a plurality of conductive traces; a processing device coupled to the printed circuit board and in electrical communication with the plurality of conductive traces; a first memory module and a second memory module in electrical communication with the plurality of conductive traces and sharing channels of the conductive traces, wherein the first memory module is physically more proximate to the processing device than is the second memory module; and an electronic band gap (EBG) structure physically disposed in an area between the first memory module and the second memory module.

Description

[0001] Cross References to Related Applications [0002] This application claims priority and benefit to U.S. Nonprovisional Application No. 15 / 659,187, filed July 25, 2017, and U.S. Provisional Patent Application No. 62 / 367,836, filed July 28, 2016, the disclosures of which The content is hereby incorporated by reference in its entirety as if fully set forth below and for all applicable purposes. technical field [0003] The present application relates to memory module electrical couplings, and in particular to electronic bandgap (EBG) structures where memory modules are electrically coupled. Background technique [0004] Some conventional systems include one or more processor chips mounted to a printed circuit board (PCB) and in communication with memory modules. Thus, in one example, a processor chip is mounted on a PCB and communicates with the memory modules through traces in the PCB. During normal operation, the processor issues read and write requests to memory. ...

AI Technical Summary

Problems solved by technology

In a daisy-chain architecture, each of the memory modules is connected to a common bus, and electromagnetic reflections can affect the capture of bits at memory modules closer to the processor

Therefore, the severity of electromagnetic reflection phenomena seen at closer memory modules can set limits on the maximum bit rate between processors in a memory module

[0006] The traditional T-topology may be used in some solutions, but if only one memory module is used on the PCB, it may be expected that the traditional T-topology will result in lower performance

Therefore, the traditional T-topology may prevent the use of a given board design in single-module applications

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