SM3 algorithm iteration system and method based on coarse granularity reconfigurable architecture

Abstract

The invention discloses a SM3 algorithm iteration system and method based on a coarse granularity reconfigurable architecture. The iteration system comprises a system bus, a reconfigurable processor and a micro-processor, wherein the reconfigurable processor comprises a configuration unit, an input first-in first-out register group, an output first-in first-out register group, a general register pile and four reconfigurable array blocks; a line inlet of the configuration unit is connected with the micro-processor through a system bus; a line outlet of the configuration unit is connected with each reconfigurable array block; the input first-in first-out register group is connected with the micro-processor through the system bus; the four reconfigurable array blocks are connected with the input / output first-in first-out register group and the general register pile respectively; data are stored, read and transmitted among the four reconfigurable array blocks through the general register pile; and the output first-in first-out register group is connected with the micro-processor through the system bus. According to the technical scheme, certain flexibility is supported, and efficient operation of a SM3 algorithm is realized through improvement on the parallel degree of the DES algorithm and optimization of the production line.

Description

technical field [0001] The invention belongs to the field of embedded reconfigurable systems, and in particular relates to a large-scale coarse-grained embedded reconfigurable system and a processing method thereof applied in the fields of communication and encryption. Background technique [0002] General-purpose processors and application-specific integrated circuits (ASICs) are two mainstream methods in the field of traditional computer system architecture. However, with the increasing demand for system performance, energy consumption, time-to-market and other indicators in the application field, the disadvantages of these two traditional computing models are exposed. [0003] The general-purpose processor method has a wide range of applications, but the calculation efficiency is low. Although the application-specific integrated circuit can improve the calculation speed and calculation efficiency and meet the performance requirements, the flexibility of the ASIC device is...

AI Technical Summary

Problems solved by technology

However, the interconnection of these arrays is relatively simple, and a large number of bit shifts and more rounds are required in the iterative operation of the SM3 algorithm, so the efficiency and speed of the operation are low

Traditional reconfigurable computing systems have big problems in SM3 computing efficiency and computing cycle

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