A 3D stacked image sensor

Abstract

The invention discloses a 3D stacked image sensor, which includes a pixel array, an analog-to-digital conversion unit array and a memory array. The image sensor is composed of an upper chip and a lower chip stacked up and down. The pixel array includes a plurality of pixel units for converting light signals into analog electrical signals, which are located on the upper chip. The analog-to-digital conversion unit array includes a plurality of analog-to-digital conversion units for converting the analog electrical signal into a digital electrical signal, which are located in the lower chip. The memory array includes a memory cell array and a logic circuit array, the memory cell array includes a plurality of memory cells for storing converted digital electrical signals, and the logic circuit array includes a plurality of memory cells for controlling the plurality of memory cells Logic circuits for cell read and write. Wherein the memory cell array is located on the upper chip and below the pixel array, and the logic circuit array of the memory array is located on the upper chip or the lower chip. The invention can improve the frame rate of the image sensor.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a 3D stacked CMOS image sensor. Background technique [0002] With the development of CMOS integrated circuit technology, the application of electronic products in daily life is becoming more and more extensive. Provided essential technical support. In practical applications, high frame rate image sensors can provide more accurate and real-time image information, and can play an important role in areas such as intelligent driving, rapid identification, and precise capture. However, in existing products, since the image data is read out and transmitted row by row, the frame rate of the image sensor is determined by the conversion and readout time of each row of data and the number of rows. For the current high-definition large pixel array, due to the constraints of the row time and the total number of rows The frame rate is greatly limited. [0003] High integration and...

AI Technical Summary

Problems solved by technology

However, the current double-layer 3D stacked chip still adopts the method of reading out row by row or multi-row in groups. Because the data transmission speed is relatively slow, after the previous frame image is exposed, the data of the next frame image must be waited until the data transmission is completed. Therefore, although the existing double-layer 3D stacked chips have improved integration, the frame rate has not been greatly improved due to the limited chip area.

Images