Parallel data processing method and device based on FPGA

A data processing device and data processing technology, applied to computer equipment and readable storage media, in the field of parallel data processing based on FPGA, can solve problems such as increasing system coupling, program flow complexity, and consuming systems, and improve data transmission Efficiency, the effect of reducing excessive waste

Active Publication Date: 2019-05-14
成都汇蓉国科微系统技术有限公司
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Problems solved by technology

However, in the parallel signal processing architecture composed of multiple DSP+FPGA in the prior art, it not only consumes huge system DDR resources and DSP computing group resources (time), but also increases the coupling degree of the system and the complexity of the program flow

Method used

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  • Parallel data processing method and device based on FPGA
  • Parallel data processing method and device based on FPGA
  • Parallel data processing method and device based on FPGA

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Embodiment 2

[0074] Step 201: Preprocessing multiple analog or digital signals from hardware modules;

[0075] Step 203: start multiple SRIO modules;

[0076] Step 205: Distributing data to multiple SRIO modules in parallel;

[0077] Step 207: Send the data transmitted by the multiple SRIOs to the DSP computing group in parallel.

[0078] Step 209: the multiple SRIO modules send a Doorbell message to the corresponding DSP computing group to inform the DSP computing group of the current data packet status.

[0079] Finally, the FPGA-based data processing system includes a step: DSP receives the data frame.

[0080] The SRIO module of the DSP receives the Doorbell message, that is, a frame of data is received, and the DSP enters the interrupt service program to check the status of the data packet.

[0081] The DSP assembles the received data frame into a complete data packet according to certain rules, and the assembly rule can be selected: through the position index of the circular queue...

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Abstract

The invention discloses a parallel data processing method and device based on an FPGA. The FPGA-based parallel data processing method comprises the following steps: preprocessing a plurality of pathsof analog or digital signals from a hardware module; starting a plurality of SRIO modules; distributing data to the plurality of SRIO modules in parallel; and sending the data transmitted by the plurality of SRIOs to a DSP computing group in parallel. The data transmission interface between the FPGA and the DSP is provided with a plurality of SRIO transmission channels; the FPGA sends the same data frame to a plurality of DSP calculation groups through SRIO at the same time; The FPGA sends the data frames according to the circular queue, and the DSP computing group selects the corresponding data packet from the circular queue for processing, so that the data transmission efficiency between the FPGA and the DSP computing group is effectively improved, and excessive waste of DDR3 resources is reduced.

Description

technical field [0001] The present invention relates to the technical field of digital signal processing, in particular to an FPGA-based parallel data processing method, device, computer equipment and readable storage medium. Background technique [0002] At present, digital signal processing equipment has been widely used in voice signal processing, image signal processing and other fields, but it also faces severe technical challenges - greater calculation, more data exchange, more complex signal algorithms, more stringent real-time requirements. [0003] Take SAR radar as an example. The number of sampling points NRN in the range direction of the SAR echo image is 4096, the number of sampling points NAN in the azimuth direction is 2048, the number of bytes occupied by each sampling point is 8 (single-precision complex points), and the maximum synthetic aperture time is 0.5s. Then there are: the amount of data required for a single signal algorithm is 512M bits, data tra...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/17
Inventor 张重九王驰汪宗福
Owner 成都汇蓉国科微系统技术有限公司
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