A device for correcting read timing of processor bm3803

Abstract

The invention discloses a device for correcting the reading sequence of the processor BM3803. The rising edge of the system clock CLK is used to drive the latch 54AC374, and the cutting edge of the chip selection signal IOSN and the address line ADDR is intercepted to obtain IOSN2 and ADDR2. The selection signal IOSN2 is intercepted at the trailing edge to obtain IOSN3, and IOSN3 and ADDR2 finally participate in decoding, so that the modified chip selection signal IOSN3 has been completely enveloped by the address line ADDR2. When the decoder is used to expand the I / O chip selection signal , which can effectively avoid the wrong output of the decoder.

Description

technical field [0001] The invention belongs to the technical field of on-board computers, and in particular relates to a device for correcting the read timing of a processor BM3803. Background technique [0002] The domestic aerospace processor BM3803 has only one I / O chip select signal (IOSN), which is far from meeting the requirements of the computer system for the number of chip select signals. It is necessary to use a decoder to expand the number of I / O chip select signals. The chip select signal is used as the enable control signal of the decoder, and the address line is used as the decoding input of the decoder. Due to the inherent timing characteristics of the BM3803, at the end of the read operation for the I / O area address, the I / O area chip select signal and the address line (ADDR) of the BM3803 are almost cancelled at the same time. See figure 2 The phase relationship between ADDR and IOSN in . If the multi-bit address line ADDR and chip select signal IOSN of B...

AI Technical Summary

Problems solved by technology

[0003] If the chip selection output by the decoder is used to perform FIFO operation, clear or reset, once a wrong chip selection occurs, it may cause malfunction and needs to be avoided

When designing the system based on the read timing of the I / O area of ​​the BM3803, in order to avoid malfunctions, it must be ensured that the address line will not change before the chip select signal at the end of the read operation, which requires full consideration of system delay and signal delay. Load conditions, and special consideration needs to be given to delay changes in high and low temperature conditions, and it is difficult to design high reliability computer systems

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