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Semiconductor device and method of forming the same

A technology for semiconductors and devices, applied in the field of semiconductor devices and their formation, can solve the problem that the performance of semiconductor devices needs to be improved, and achieve the effects of improving performance, increasing driving current, and reducing resistance

Active Publication Date: 2022-02-15
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the performance of semiconductor devices composed of existing fin field effect transistors needs to be improved

Method used

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  • Semiconductor device and method of forming the same
  • Semiconductor device and method of forming the same
  • Semiconductor device and method of forming the same

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0029] As mentioned in the background, semiconductor devices formed by the prior art have poor performance.

[0030] A method for forming a semiconductor device, comprising: providing a semiconductor substrate with a fin and an isolation structure covering a sidewall of a part of the fin; forming a gate structure across the fin on the isolation structure, the gate structure Covering part of the top surface and part of the sidewall surface of the fin; forming spacers across the fins on the sidewalls on both sides of the gate structure; forming source-drain doping in the first gate structure and the fins on both sides of the spacers Area.

[0031] However, the performance of the semiconductor device formed by the above method is poor, and it is found through research that the reasons are:

[0032] The spacers are used to define the distance between the gate structure and the source and drain doped layers. In order to improve the driving current of the semiconductor device, one...

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Abstract

A semiconductor device and its forming method, wherein the semiconductor device includes: a semiconductor substrate; a fin located on the semiconductor substrate; an isolation structure located on the semiconductor substrate and covering part of the sidewall of the fin; located on the isolation structure and spanning The first gate structure of the fin, the first gate structure covers part of the top surface and part of the sidewall surface of the fin; the sidewalls on both sides of the first gate structure and across the sidewall of the fin, the sidewall includes the bottom The side wall area and the top side wall area, the bottom side wall area is located on the surface of the isolation structure and covers part of the side wall of the first gate structure and part of the side wall of the fin, the top of the bottom side wall area is lower than the top surface of the fin, and the top side The wall region is located on the bottom sidewall region and on the top surface of the fin, the thickness of the bottom sidewall region is greater than the thickness of the top sidewall region; the source and drain doping regions are located in the first gate structure and the fins on both sides of the sidewall. The performance of the semiconductor device is improved.

Description

technical field [0001] The present invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a method for forming the same. Background technique [0002] MOS transistors are one of the most important components in modern integrated circuits. The basic structure of a MOS transistor includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, a source region located in the semiconductor substrate on one side of the gate structure, and a drain region located in the semiconductor substrate on the other side of the gate structure. The working principle of a MOS transistor is to apply a voltage to the gate structure to generate a switching signal by adjusting the current in the channel at the bottom of the gate structure. [0003] With the development of semiconductor technology, the control ability of traditional planar MOS transistors on channel current is weakened, resulting in ser...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L21/336
Inventor 周飞
Owner SEMICON MFG INT (SHANGHAI) CORP