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Frequency discriminator, PAM4 clock data frequency locking method, recovery method and circuit

A clock data recovery, frequency locking technology, applied in the direction of electrical components, automatic power control, etc., can solve the problem of unable to lock the frequency, the output gain of the frequency discriminator is reduced, and the frequency is falsely locked.

Active Publication Date: 2019-05-21
PHOTONIC TECH SHANGHAI CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In view of the above-mentioned shortcoming of the prior art, the object of the present invention is to provide a kind of discriminator, PAM4 clock data frequency locking method, recovery method and circuit, for solving the PAM4 clock data recovery circuit without reference clock in the prior art Unable to lock frequency, frequency false lock, frequency discriminator output gain reduction or polarity inversion, etc.

Method used

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  • Frequency discriminator, PAM4 clock data frequency locking method, recovery method and circuit
  • Frequency discriminator, PAM4 clock data frequency locking method, recovery method and circuit
  • Frequency discriminator, PAM4 clock data frequency locking method, recovery method and circuit

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Embodiment 1

[0099] Such as Figure 1 to Figure 5 As shown, the present embodiment provides a PAM4 clock data recovery circuit 1, and the PAM4 clock data recovery circuit 1 includes:

[0100] Sampler 11 , frequency discriminator 12 , controller 13 , phase detector 14 , first charge pump 15 , second charge pump 16 , loop filter 17 and voltage controlled oscillator 18 .

[0101] Such as figure 1 As shown, the sampler 11 receives the input signal, the data sampling clock CK1 and the edge sampling clock CK2, and based on the first sampling CK1 and the edge sampling clock CK2, the data of the fourth-order pulse amplitude modulation signal PAM4 and the The edge is sampled to obtain the sampling data D and the sampling edge E.

[0102] Specifically, the sampler 11 includes a plurality of sampling units for sampling the input signal data and edges based on different reference values. In this embodiment, the input signal is a fourth-order pulse amplitude modulation signal PAM4. Since the fourth-...

Embodiment 2

[0128] Such as Figure 2 to Figure 19 As shown, the present embodiment provides a PAM4 clock data recovery method. In this embodiment, the PAM4 clock data recovery method is implemented based on the PAM4 clock data recovery circuit 1. In practical applications, the PAM4 clock data recovery The method can be implemented based on any hardware circuit or software code that can realize the method, and details will not be repeated here. The PAM4 clock data recovery method comprises:

[0129] 1) Open loop frequency approximation.

[0130] Specifically, in the start-up phase, the frequency difference between the sampling clock and the fourth-order pulse amplitude modulation signal PAM4 is large, and the controller 13 configures the PAM4 clock data recovery circuit 1 in an open-loop frequency approximation mode, that is, the first A charge pump 15 , the second charge pump 16 and the loop filter 17 are all in an off state.

[0131] Specifically, the voltage-controlled oscillator 18 ...

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Abstract

The invention provides a frequency discriminator, a PAM4 clock data frequency locking method, a PAM4 clock data frequency recovery method and a PAM4 clock data frequency locking circuit. The method comprises the following steps: respectively sampling data and edges of an input signal by adopting a data and edge sampling clock; Obtaining a logic result of the speed of the sampling clock according to the sampling data of at least two adjacent clock periods and the sampling edge between the two sampling data; Determining the frequency of the sampling clock relative to the input signal based on the logic results of at least three adjacent clock periods, and enabling the frequency of the sampling clock to be equal to that of the input signal; based on the Bang-Bang logics, adjusting the phase of the sampling clock, so that the sampling edge of the sampling clock is respectively positioned in the data of the input signal and the middle area of the edge. The non-reference clock frequency locking and phase locking technology is adopted, so that the frequency and the phase can be accurately locked; The requirement for the frequency difference between the starting frequency of the voltage-controlled oscillator and an input signal is low, the clock data recovery function of the large-range input data rate can be supported, the application range is wide, and the stability is high.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a frequency discriminator, a PAM4 clock data frequency locking method, a recovery method and a circuit. Background technique [0002] Clock data recovery, as the core function that high-speed serial communication must have, has been more and more widely used. Clock data recovery is to extract the clock signal from the data signal according to the reference clock. Correspondingly, only serial data is transmitted on the channel without a clock signal, and the data receiving end receives the serial data and performs clock recovery. Obviously, being able to accurately recover the clock signal from the data is the key to this technology. [0003] In the prior art, a PAM4 clock data recovery circuit without a reference clock is proposed. When the difference between the initial frequency of the voltage-controlled oscillator and the frequency of the input data signal exceeds th...

Claims

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Application Information

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IPC IPC(8): H03L7/08H03L7/089H03L7/091H03L7/093H03L7/099H03L7/113
Inventor 王心白睿夏韬彭毅陈学峰
Owner PHOTONIC TECH SHANGHAI CO LTD
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