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A qr31 code decoding method based on fpga

A QR31 and QR code technology, applied in the field of channel error correction codes, can solve problems such as speed restrictions, and achieve the effect of increasing operating frequency and decoding speed

Active Publication Date: 2021-05-18
HANGZHOU DIANZI UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In practical applications, the cycle characteristics of QR codes are often used, and the cpu decoding method is used. Due to the sequential execution characteristics of the software, there is a certain limit in speed.

Method used

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  • A qr31 code decoding method based on fpga
  • A qr31 code decoding method based on fpga
  • A qr31 code decoding method based on fpga

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Embodiment Construction

[0030] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0031] On the contrary, the invention covers any alternatives, modifications, equivalent methods and schemes within the spirit and scope of the invention as defined by the claims. Further, in order to make the public have a better understanding of the present invention, some specific details are described in detail in the detailed description of the present invention below. The present invention can be fully understood by those skilled in the art without the description of these detailed parts.

[0032] see figure 1 , is a flow chart of the steps of the embodiment of the present invention, the te...

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Abstract

The invention discloses a QR31 code decoding method based on FPGA, which includes the following steps: S10, a data selection module converts a received codeword into three different codewords; S20, respectively sends it into three pipelines for parallel decoding; S30, data The selection module finally outputs the decoding result according to the decoding situation; in the S20, the three parallel pipelines all include two steps, and each step includes two units: a syndrome checking unit and an error correction unit, wherein the The syndrome checking unit is used to generate a series of different syndromes, and check whether these syndromes meet the decoding conditions; the error correction unit receives the instruction sequence from the syndrome checking unit, and decides whether to trigger decoding. The present invention realizes high-speed parallel decoding by decomposing the whole decoding process into independent three-way decoding processes.

Description

technical field [0001] The invention belongs to the field of channel error correction codes, and relates to an FPGA-based QR code decoding method. Background technique [0002] In recent years, technologies such as the Internet of Things and the Internet of Vehicles have gradually emerged. In the application scenarios of these technologies, the length of the instruction data packet in the wireless channel is relatively short, and the reliability requirements are high. Error correction coding. QR code (Quadratic Residue code, square residual code), as an efficient short code error correction code, is adopted in the field of short frame communication because of its large minimum Hamming distance and strong error correction ability. In practical applications, the cycle characteristics of QR codes are often used, and the cpu decoding method is used. Due to the sequential execution characteristics of the software, there is a certain limit in speed. Contents of the invention ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L1/00H03M13/15
Inventor 黄继业刘鹏谢尚港张新球周涛
Owner HANGZHOU DIANZI UNIV