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Low voltage high sigma multi-port memory control

A technology of memory controller and memory, which is applied in the direction of static memory, digital memory information, information storage, etc., and can solve problems such as functional failure and low output of multi-port memory systems

Active Publication Date: 2019-06-25
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Variations between pulse latches can cause functional failures, leading to low yield in multi-port memory systems configured with low-voltage operation

Method used

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  • Low voltage high sigma multi-port memory control
  • Low voltage high sigma multi-port memory control
  • Low voltage high sigma multi-port memory control

Examples

Experimental program
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Embodiment Construction

[0020] The detailed description set forth below with respect to the accompanying figures is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts. Acronyms and other descriptive terms may be used for convenience and clarity only and are not intended to limit any concepts disclosed herein.

[0021] The various memories presented throughout this disclosure may be implemented as or in separate memories. These aspects may also be included in an integrated circuit (IC) or system, or a portion the...

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Abstract

In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory controller that includes a logic circuit configured to generate a select signal for selecting betweenfirst and second ports of a memory as a function of first and second port signals. Additionally, the memory controller includes a switch configured to connect and disconnect the first and the secondport signals. In another aspect of the disclosure, the apparatus is a storage apparatus that includes a memory and a memory controller. The memory controller includes a latch configured to latch a first port selection signal to produce a first port signal and latch a second port selection signal to produce a second port signal. The memory controller also includes a switch configured to connect anddisconnect the first and the second port signals and a logic circuit configured to generate a select signal.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of U.S. Patent Application No. 15 / 352,197, filed November 15, 2016, entitled "LOW VOLTAGE HIGH SIGMA MULTI-PORTMEMORY CONTROL," which is expressly incorporated herein by reference in its entirety. technical field [0003] The present disclosure relates generally to memory circuitry and, more particularly, to memory control circuitry. Background technique [0004] An example static random access memory (SRAM) cell may include pairs of cross-coupled inverters, eg, each formed from a pair of transistors. Cross-coupled inverters can be used to store bits in one of two stable logic states (eg, logic "1" or logic "0"). Each pair of transistors that may form an inverter may be a P-type metal-oxide-semiconductor (PMOS) transistor and an N-type metal-oxide-semiconductor (NMOS) transistor. By using a combination of PMOS and NMOS transistors, static power consumption can be reduced because i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/10G11C8/16G11C11/418G11C11/419G06F13/16
CPCG06F13/1668G11C7/1075G11C8/16G11C2207/2209Y02D10/00G11C11/419G11C11/418
Inventor T·C·Y·郭晶昌镐
Owner QUALCOMM INC