nand type rom

Abstract

The invention discloses an NAND type ROM. A column structure comprises a plurality of NAND type memory cell series structures and bit lines. Each storage unit series structure is connected between thecorresponding bit line and the corresponding source line; each memory cell series structure in the row structure forms a corresponding memory cell series structure row; the source lines form a dynamic split type source electrode bias voltage structure, and specifically, any two adjacent storage unit series structures in the storage unit series structure row are connected with different source lines; source lines connected with different memory cell series structures in the same column are different. The bias voltage in the reading process is set as follows: the source line corresponding to the read memory cell is connected with a low level, the source line corresponding to the memory cell series structure adjacent to the read memory cell in the same row is connected with a high level, andthe source line corresponding to the memory cell series structure adjacent to the read memory cell in the same column structure is connected with a high level. The reading voltage drop caused by bitline electric leakage, bit line capacitance sharing and bit line crosstalk can be eliminated.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a NAND type read-only memory (ROM). Background technique [0002] Such as Figure 1A Shown is the array structure 101 diagram of the existing NAND type ROM, Figure 1B yes Figure 1A In the serial structure diagram of memory cells in , the existing NAND-type ROM includes an array structure 101 formed by a plurality of memory cells 102 arranged in rows and columns, and the column structure 104 of the array structure 101 includes: [0003] A plurality of NAND-type memory cells are connected in series (string) structure 103 and a bit line. Figure 1A In the above, the bit line is represented by BL, and the bit line of different columns is represented by the number of columns, such as BL[0], BL[1], BL[2], BL[3], BL[4], BL[5] Show. [0004] Such as Figure 1B As shown, each storage unit series structure 103 is formed by a selection transistor 106 and a plurality of storage unit...

AI Technical Summary

Problems solved by technology

With the reduction of the operating voltage, that is, the power supply voltage, the reading voltage of the bit line caused by the leakage of the bit line drops very severely, especially in the FF process corner and high temperature conditions such as 125°C. The reading voltage of the bit line caused by the leakage of the bit line is very serious.

[0029] like Figure 2B As shown, it is a schematic diagram of the reduction of the bit line voltage caused by the bit line charge sharing of the existing NAND type ROM. Figure 2B Take the reading of the storage unit 102 in the storage unit series structure corresponding to the dotted line box 103c as an example for illustration. It can be seen that each of the storage units 102 in the storage unit series structure 103c between the drain and the low has a parasitic capacitance C CS , during the read process, the capacitance C corresponding to the bit line BL[0] BS The stored charge will be shared to the capacitor C CS In this way, the voltage of the bit line BL[0] will drop

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