Two-terminal vertical type 1t-dram and manufacturing method therefor

Abstract

A two-terminal vertical type 1T-DRAM and a manufacturing method therefor are disclosed. According to one embodiment of the present invention, the two-terminal vertical type 1T-DRAM comprises: a cathode layer formed as a first-type high-concentration semiconductor layer; a base region including a second-type low-concentration semiconductor layer formed on the cathode layer and a first-type low-concentration semiconductor layer formed on the second-type low-concentration semiconductor layer; and an anode layer formed as a second-type high-concentration semiconductor layer on the first-type low-concentration semiconductor layer.

Description

technical field [0001] The present invention relates to a two-terminal vertical type 1T-dynamic random access memory and its manufacturing method. Thyristor-based two-terminal vertical type 1T-Dynamic random access memory and method of manufacturing the same based on the doping concentration of the base region to perform memory operations. Background technique [0002] According to the prior art, a dynamic random access memory (DRAM) memory cell consists of a metal oxide semiconductor field effect transistor (Metal Oxide Silicon Field Effect Transistor, n-MOSFET) and a cylindrical (cylinder type) capacitor Composed of (capacitor), the design rules of DRAM storage unit transistors (for example: gate length) have reached the 20nm level, and the height of the cylindrical capacitor is about 1.5um, and has achieved up to 64 gigabytes (Giga Byte) ) integration. [0003] However, in order to make the integration level of the DRAM memory cell 1 terabit, it is necessary to form the...

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Problems solved by technology

[0009] Moreover, in the 1T-DRAM based on the 3-terminal thyristor, when the p-base area is high (high), it can cause a latch-up effect to make the read state "1", and in the p-base area When it is low (low), it can cause blocking (blocking) so that the read status becomes "0"

[0010] Since the conventional 1-T DRAM based on the 3-terminal thyristor requires a gate terminal for applying current to the base region and is formed horizontally, it requires a large area, so there is a limitation in scaling down

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