3D NAND memory device and manufacturing method thereof

Abstract

The invention provides a 3D NAND memory device and a manufacturing method thereof. A substrate is provided firstly; a barrier layer and a first stacking layer are sequentially formed on the substrate,wherein the first stacking layer is formed by alternately laminating an insulating layer and a sacrificial layer; the barrier layer is used as an etching stop layer; the first stacking layer is etched to form a channel hole; and the barrier layer at the bottom of the channel hole is removed, and etching of the channel hole is completed. In the embodiments of the invention, during the etching process of the first stacking layer, the barrier layer protects the substrate, so that after the barrier layer is removed, the substrate is not damaged, and therefore the subsequent processes are reduced,and the performance of the device is improved.

Description

technical field [0001] The present invention relates to the semiconductor field and its manufacturing field, in particular to a 3D NAND memory device and its manufacturing method. Background technique [0002] NAND storage devices are non-volatile storage products with low power consumption, light weight and good performance, and are widely used in electronic products. Planar NAND devices are close to the limit of practical expansion. In order to further increase storage capacity and reduce storage cost per bit, 3D NAND storage devices are proposed. In the 3D NAND storage device structure, a stacked storage device structure is realized by vertically stacking multi-layer data storage units. [0003] In the manufacturing process of 3D NAND, such as figure 1 As shown, now a stacked layer 110 of an insulating layer 1101 and a sacrificial layer 1102 is formed on the substrate 100, a channel hole 120 penetrating through the stacked layer is formed in the stacked layer 110, and a...

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Problems solved by technology

[0004] In the prior art, when the channel hole 120 penetrating the stack layer 110 is formed in the stack layer 110, it is usually realized by anisotropic dry etching, but the etching uniformity of the channel hole 120 cannot be guaranteed, and at the same time It will cause damage to the substrate 100 under the stacked layer 110, affecting subsequent processes and device performance

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