Post-binding through silicon via test structure and method specific to through silicon via electric leakage fault

Abstract

The invention discloses a post-binding through silicon via test structure and method specific to a through silicon via electric leakage fault, relates to the field of integrated circuit test, and aimsto solve the problems of low measurement accuracy, low measurement error in case of an error fault and incapability of determining a fault point in a conventional through silicon via test structure.The post-binding through silicon via test structure and method specific to the through silicon via electric leakage fault comprises a conventional through silicon via test circuit based on a ring oscillator, and a RC circuit used for lowering the frequency of the ring oscillator. Specific to the post-binding test of a through silicon via, the detected fault is determined as the electric leakage fault of the through silicon via. When the through silicon via is connected, the signal outputting period of the test structure is more sensitive to the electric leakage fault of the through silicon via, so that the test cost is lowered, and the influence of the diagnosis result on the measurement error is smaller. The post-binding through silicon via test structure is suitable for detecting micro electric leakage area.

Description

technical field [0001] The invention belongs to the field of integrated circuit testing. Background technique [0002] Moore's Law predicts that when the price remains constant, the number of components that can be accommodated on an integrated circuit will double approximately every 18-24 months. This trend has been going on for half a century, but as the physical size of complementary metal-oxide-semiconductor (CMOS) transistors is gradually approaching the limit, it is no longer reasonable to rely solely on reducing the size of transistors to improve the performance of integrated circuits. Therefore, relying on shrinking transistor size to improve integrated circuit performance and reduce power consumption has become unfeasible. The traditional two-dimensional integrated circuit process can no longer meet the requirements of today's industry for high processing speed and low power consumption of integrated circuits. Three-dimensional integrated circuits are considered t...

AI Technical Summary

Problems solved by technology

[0008] The present invention aims to solve the problems of low measurement accuracy of the traditional TSV test structure, small measurement error when there is an error fault, and failure to determine the fault point, and now provides a bonded TSV test for TSV leakage faults structure and method

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