Low-power-consumption multiplier based on 4-Booth coding

Abstract

The invention discloses a low-power-consumption multiplier based on 4-Booth coding. The multiplier comprises an encoder group formed by connecting at least two encoders in parallel. The input end of the encoder group is connected with a bit selector. The input end of the bit selector is connected with a multiplier input port and a multiplicand input port. First Power gating switches are respectively connected between the input end of the bit selector and the multiplier input port and between the input end of the bit selector and the multiplicand input port of the multiplicand. The output end of the encoder group is connected with the input end of the compressor through the second Power gating switch, and the output end of the compressor is connected with the input end of the super-forwardadder through the third Power gating switch. The low-power-consumption multiplier based on 4-Booth coding disclosed by the invention can reduce power consumption while ensuring an accurate calculationresult.

Description

technical field [0001] The invention belongs to the technical field of low-power multipliers, in particular to a low-power multiplier based on 4-Booth coding. Background technique [0002] In various chips such as high-speed digital signal processing (DSP), microprocessor (MCU) and RISC, the multiplier is an indispensable unit, and the multiplier is often in the critical path, so the speed of the system often depends on the multiplier speed. In order to achieve the normal operation of the pipeline, the multiplier in the execution unit needs to be completed within one clock cycle. The operation efficiency and stability of the whole processor can be influenced and improved by optimizing the design of the multiplier. Therefore, the design of a high-speed, portable and low-power multiplier is a very important and necessary part of system design in the field of application-specific integrated circuits, digital signal processing, and digital filtering. [0003] One implementati...

AI Technical Summary

Problems solved by technology

In this case, according to conventional encoding, compression, and summation, not only waste a lot of time but also occupy a lot of hardware resources, which increases the power consumption of the entire system

[0004] In addition, when the multiplier circuit performs the multiplication operation, the encoding unit, the compression unit, and the carry-ahead adder unit are serially connected. When the front-stage circuit has not completed the operation, the subsequent-stage circuit is always in a waiting state. Although the circuit is turned on, the Does not participate in the calculation, increasing the power consumption of the system

When the partial product enters the compression unit to participate in the summation operation, due to the difference in the generation delay between the carry signal and the partial product signal, when it enters the next-level Wallace tree compression circuit, there may be a risk of competition that leads to erroneous calculation results

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