Light-emitting element drive circuit

Abstract

A light-emitting element driving circuit, comprising: a power conversion circuit, an error amplification circuit, a sampling and holding circuit, a load current generating circuit and a feed-forward capacitor. During the non-enabled phase, the feedback signal is electrically connected to the second reference voltage through the sample-and-hold circuit and is disconnected from the load node, thereby, at the transition time point from the non-enabled phase to the enabled phase, the feed-forward The capacitor samples a sampled voltage. In the enable phase, the feedback signal is disconnected from the second reference voltage through the sample-and-hold circuit and coupled to the load node, and the sample voltage is maintained through the feed-forward capacitor, so that within the preset current rise time after the turning point , the difference between the feedback signal and the first reference voltage is large enough, so that the load current rises to reach the first current level within a predetermined current rising time.

Description

technical field [0001] The present invention relates to a light-emitting element driving circuit, in particular to a method of improving the load-transient response of the light-emitting element driving circuit through a sample-and-hold circuit, so that the load current can rise rapidly within a preset current rising time , to drive the light-emitting element to achieve the target current level. Background technique [0002] Please refer to figure 1 and figure 2 . figure 1 Mark the schematic diagram of the light-emitting element driving circuit in the prior art. figure 2 A schematic diagram of the waveform of the operating signal of the light-emitting element driving circuit in the prior art is marked. [0003] In the light-emitting element driving circuit 100 of the prior art, when the light-emitting element driving circuit 100 is in the non-enabled phase (that is, when the enable signal EN is at a low level), the level of the load current iLOAD is zero, and at this t...

AI Technical Summary

Problems solved by technology

During the time T1, the load current iLOAD can only draw current from the capacitor C2, however, such a current level is still very low (eg figure 2 The waveform diagram of the load current Iload within the time T1 shown)

[0004] In addition, in the prior art, the load current iLOAD is related to the level of the feedback signal FB. Therefore, another major disadvantage of the prior art is: when the feedback signal FB drops below the reference voltage VREF (such as but not limited to 0.2V ) level is still low, due to excessive overshoot (overshoot) effect, the feedback signal FB may be as low as but not limited to 0.1V, because the load current iLOAD is related to the level of the feedback signal FB, therefore, too low feedback The signal FB level will also cause the load current iLOAD to fail to quickly reach its target current level Ip, where the target current level Ip is, for example, the load current level corresponding to the feedback signal FB being 0.2V

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